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technical manual usb2.0 device controller S1R72003 mf1495 - 02
notice no part of this material may be reproduced or duplicated in any form or by any means without the written permission of seiko epson. seiko epson reserves the right to make changes to this material without notice. seiko epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. this material or portions thereof may contain technology or the subject relating to strategic products under the control of the foreign exchange and foreign trade law of japan and may require an export license from the ministry of international trade and industry or other approval from anther government agency. ?seiko epson corporation 2002, all rights reserved. all other product names mentioned herein are trademarks and/or registered trademarks of their respective companies.
the information of the product number change starting april 1, 2001 the product number has been changed as listed below. please use the new product number when you place an order. for further information, please contact epson sales representative. configuration of product number z devices s1 r 72803 f 00a1 00 packing specifications specifications shape (f : qfp) model number model name ( r:exclusive use controller,peripheral ) product classification (s1:semiconductors)
epson i contents 1. description................................................................................................................. ................... 1 2. features .................................................................................................................... ..................... 1 3. block diagram ............................................................................................................... .............. 2 4. pin assignment .............................................................................................................. ............... 3 5. pin description ............................................................................................................. ............... 4 5.1 cpu interface.............................................................................................................. ............... 4 5.2 ide/general-purpose port interface ......................................................................................... .5 5.3 usb interface .............................................................................................................. ............... 6 5.4 system blocks and others................................................................................................... ...... 6 5.5 test signals ............................................................................................................... ................. 7 5.6 power supply and gnd ....................................................................................................... ...... 7 6. functional description...................................................................................................... ..... 8 6.1 utmi1.0 transceiver macro.................................................................................................. ..... 8 6.2 serial interface engine.................................................................................................... ........... 8 6.2.1 packet handler........................................................................................................... .. 8 6.2.2 transaction manager ................................................................................................... 8 6.2.3 endpoints................................................................................................................ ...... 8 6.2.4 suspend/resume controller ........................................................................................ 8 6.3 fifo sram.................................................................................................................. .............. 8 6.4 fifo controller............................................................................................................ ............... 8 6.5 dma........................................................................................................................ .................... 8 6.6 test/debug module .......................................................................................................... .......... 8 7. register.................................................................................................................... ...................... 9 7.1 register map ............................................................................................................... ............... 9 7.2 register details........................................................................................................... ............. 15 7.2.1 00h main interrupt status (mainintstat) ................................................................ 15 7.2.2 01h sie interrupt status (sieintstat) .................................................................... 16 7.2.3 02h bulk interrupt status (bulkintstat).................................................................. 17 7.2.4 03h epr interrupt status (eprintstat).................................................................... 18 7.2.5 04h ide interrupt status (ideintstat).................................................................... 19 7.2.6 05h reserved ........................................................................................................ 19 7.2.7 06h port interrupt status (portintstat)................................................................... 20 7.2.8 07h reserved ........................................................................................................ 20 7.2.9 08h ep0 interrupt status (ep0intstat) .................................................................. 21 7.2.10 09h epa interrupt status (epaintstat) .................................................................. 22 7.2.11 0ah epb interrupt status (epbintstat).................................................................. 23 7.2.12 0bh epc interrupt status (epcintstat) .................................................................. 24 7.2.13 0ch to 0fh reserved ............................................................................................... 24 7.2.14 10h main interrupt enable (mainintenb) ............................................................... 24 7.2.15 11h sie interrupt enable (sieintenb) ................................................................... 25 7.2.16 12h bulk interrupt enable (bulkintenb)................................................................. 25 7.2.17 13h epr interrupt enable (eprintenb)................................................................... 25 7.2.18 14h ide interrupt enable (ideintenb)................................................................... 25 7.2.19 15h reserved ...................................................................................................... 26 7.2.20 16h port interrupt enable (portintenb).................................................................. 26 7.2.21 17h reserved ...................................................................................................... 26 7.2.22 18h ep0 interrupt enable (ep0intenb) ................................................................. 26 7.2.23 19h epa interrupt enable (epaintenb) ................................................................. 27 7.2.24 1ah epb interrupt enable (epbintenb)................................................................. 27 7.2.25 1bh epc interrupt enable (epcintenb) ................................................................. 27 7.2.26 1ch to 1fh reserved ............................................................................................. 27 7.2.27 20h chip reset (chipreset) ................................................................................. 28 7.2.28 21h revision number (revisionnum)................................................................... 28
ii epson 7.2.29 22h power management control (pmcontrol)...................................................... 29 7.2.30 23h usb control (usbcontrol) ............................................................................. 30 7.2.31 24h usb status (usbstatus)................................................................................ 31 7.2.32 25h xcvr control (xcvrcontrol) ............................................................................. 32 7.2.33 26h usb test (usbtest) ....................................................................................... 33 7.2.34 27h reserved ...................................................................................................... 34 7.2.35 28h usb address (usbaddress).......................................................................... 34 7.2.36 29h epr control (eprcontrol)................................................................................ 35 7.2.37 2ah bulkonly control (bulkonlycontrol) .............................................................. 36 7.2.38 2bh bulkonly config (bulkonlyconfig)................................................................. 37 7.2.39 2ch to 2eh reserved ............................................................................................. 37 7.2.40 2fh chip config (chipconfig) ............................................................................... 38 7.2.41 30h to 37h ep0 setup0 to ep0 setup7 (ep0setup_0 to ep0setup_7) ............... 39 7.2.42 38h framenumber high (framenumber_h) ........................................................ 39 7.2.43 39h framenumber low (framenumber_l).......................................................... 40 7.2.44 3ah to 3fh reserved ............................................................................................. 40 7.2.45 40h ep0 config_0 (ep0control_0) ....................................................................... 41 7.2.46 41h reserved ...................................................................................................... 41 7.2.47 42h ep0 control_0 (ep0control_0) ...................................................................... 42 7.2.48 43h ep0 control_1 (ep0control_1) ...................................................................... 43 7.2.49 44h reserved ...................................................................................................... 43 7.2.50 45h ep0 fifo remain (ep0fiforemain) ........................................................... 43 7.2.51 46h ep0 fifoforcpu (ep0fifoforcpu) ............................................................. 44 7.2.52 47h ep0 fifo control (ep0fifocontrol)............................................................. 44 7.2.53 48h to 4fh reserved .............................................................................................. 44 7.2.54 50h epa config_0 (epaconfig_0)......................................................................... 45 7.2.55 51h epa config_1 (epaconfig_1)......................................................................... 46 7.2.56 52h epa control_0 (epacontrol_0) ...................................................................... 47 7.2.57 53h epa control_1 (epacontrol_1) ...................................................................... 48 7.2.58 54h epa fifo remain high (epafiforemain_h).............................................. 48 7.2.59 55h epa fifo remain low (epafiforemain_l) ............................................... 48 7.2.60 56h epa fifo for cpu (epafifoforcpu) ........................................................... 49 7.2.61 57h epa fifo control (epafifocontrol)............................................................. 49 7.2.62 58h epb config_0 (epbconfig_0)......................................................................... 50 7.2.63 59h epb config_1 (epbconfig_1)......................................................................... 51 7.2.64 5ah epb control_0 (epbcontrol_0)...................................................................... 52 7.2.65 5bh epb control_1 (epbcontrol_1)...................................................................... 53 7.2.66 5ch epb fifo remain high (epbfiforemain_h) ............................................. 53 7.2.67 5dh epb fifo remain low (epbfiforemain_l)............................................... 53 7.2.68 5eh epb fifo for cpu (epbfifoforcpu)........................................................... 54 7.2.69 5fh epb fifo control (epbfifocontrol) ............................................................ 54 7.2.70 60h epc config_0 (epcconfig_0) ......................................................................... 55 7.2.71 61h epc config_1 (epcconfig_1) ......................................................................... 56 7.2.72 62h epc control_0 (epccontrol_0) ...................................................................... 57 7.2.73 63h epc control_1 (epccontrol_1) ...................................................................... 58 7.2.74 64h epc fifo remain high (epcfiforemain_h) .............................................. 58 7.2.75 65h epc fifo remain low (epcfiforemain_l)................................................ 58 7.2.76 66h epc fifo for cpu (epcfifoforcpu)............................................................ 59 7.2.77 67h epc fifo control (epcfifocontrol) ............................................................. 59 7.2.78 68h iso max packet size high (isomaxsize_h) ................................................... 59 7.2.79 69h iso max packet size low (isomaxsize_l)..................................................... 60 7.2.80 6ah to 7fh reserved ............................................................................................. 60 7.2.81 80h ide status (idestatus)................................................................................... 60 7.2.82 81h ide config_0 (ideconfig_0) .......................................................................... 61 7.2.83 82h ide config_1 (ideconfig_1) .......................................................................... 62 7.2.84 83h reserved ...................................................................................................... 64 7.2.85 84h ide register mode (ide_rmod).................................................................... 64
epson iii 7.2.86 85h ide transfer mode (ide_tmod) .................................................................... 65 7.2.87 86h ide ultra-dma transfer mode (ide_umod) .................................................. 65 7.2.88 87h reserved ...................................................................................................... 66 7.2.89 88h ide control_0 (idecontrol_0)........................................................................ 66 7.2.90 89h reserved ...................................................................................................... 67 7.2.91 8ah ide transfer byte count high (ide_count_h) ............................................. 67 7.2.92 8bh ide transfer byte count middle (ide_count_m).......................................... 67 7.2.93 8ch ide transfer byte count low (ide_count_l)............................................... 67 7.2.94 8dh ide crc control (ide_crccontrol) ............................................................ 68 7.2.95 8eh ide crc high (ide_crc_h) ........................................................................ 68 7.2.96 8fh ide crc low (ide_crc_l).......................................................................... 68 7.2.97 90h ide_cs00 (ide_cs00) .................................................................................. 69 7.2.98 91h to 9fh ide_cs01 to ide_cs17 (ide_cs01 to ide_cs17)............................. 70 7.2.99 a0h to beh cbw_00 to csw_30 (cbw_00 to cbw_30).................................... 71 7.2.100 bfh reserved ...................................................................................................... 71 7.2.101 c0h to cch csw0_00 to csw0_12 (csw0_00 to csw0_12) ........................... 71 7.2.102 cdh to cfh reserved ............................................................................................ 72 7.2.103 d0h to dch csw1_00 to csw1_12 (csw1_00 to csw1_12) ........................... 72 7.2.104 ddh to dfh reserved ............................................................................................ 72 7.2.105 e0h port direction (portdir)................................................................................... 73 7.2.106 e1h port data (portdata) ...................................................................................... 73 8. typical connections ......................................................................................................... ...... 74 8.1 example of connecting usb interface and other pins ........................................................... 74 8.2 example of connecting ide interface and other pins ............................................................ 75 8.3 examples of connection of ide i/f pins (when general-purpose dma is used).................. 76 8.4 example of connecting cpu interface and other pins .......................................................... 77 9. electrical characteristics................................................................................................ 78 9.1 absolute maximum ratings ................................................................................................... .. 78 9.2 recommended operating conditions...................................................................................... 78 9.3 dc characteristics ......................................................................................................... .......... 79 9.4 ac characteristics ......................................................................................................... .......... 81 9.4.1 cpu i/f access timing .............................................................................................. 81 9.4.2 ide i/f timing........................................................................................................... .. 83 9.4.3 general-purpose port i/f timing................................................................................ 90 9.4.4 usb i/f timing ........................................................................................................... 94 10. external package........................................................................................................... ......... 95 appendix-a. usb operation other than transfer.......................................................... 96 a.1 suspend detection......................................................................................................... .......... 96 a.1.1 suspend detection (hs mode).................................................................................... 96 a.1.2 suspend detection (fs mode) .................................................................................... 98 a.2 reset detection ........................................................................................................... ............ 99 a.2.1 reset detection (hs mode) ........................................................................................ 99 a.2.2 reset detection (fs mode)....................................................................................... 100 a.3 hs detection handshake .................................................................................................... ..101 a.3.1 when this ic is connected to fs downstream port................................................ 102 a.3.2 when this ic is connected to hs downstream port ............................................... 104 a.3.3 when this ic is reset in snooze.............................................................................. 106 a.4 issue of resume ........................................................................................................... ......... 108 a.5 detection of resume ....................................................................................................... ...... 111 a.6 cable insertion........................................................................................................... ............ 113 a.7 clock ..................................................................................................................... ................. 115 a.7.1 start of oscillator circuit............................................................................................ 1 15 a.7.2 sleep (stop of oscillator circuit) ............................................................................... 117
iv epson a.7.3 pll switching ........................................................................................................ 118 appendix-b. recommended oscillator circuit .............................................................. 119
S1R72003 technical manual rev.1.0 epson 1 1. description the S1R72003f00b100 is a general-purpose usb device controller lsi that supports the usb 2.0 high-speed mode. with the field-proven, utmi rev 1.0-compliant transceiver circuit, it assures connectivity of usb devices. 2. features ? supports hs (480mbps) and fs (12mbps) transfers. ? supports control, bulk, interrupt, and isochronous transfers. ? supports three general-purpose endpoints and endpoint 0. ? contains a 2.5-kb programmable fifo for endpoint use. ? incorporates ide and general-purpose dma ports. ide: supports pio modes 1/2/3/4. supports multiword dma modes 0/1/2. supports ultra-dma modes 1/2/3/4. general-purpose dma: the bus width can be set to 8 or 16 bits. both master and slave are supported. ? incorporates an 8-bit, general-purpose cpu interface. ? accommodates 12, 16, 20, and 24-mhz crystal resonators for clock input. ? multiple power management mode snooze: pll halt mode triggered by detection of the suspend state of usb. sleep: oscillation circuit halt mode triggered by xsleep pin assertion. ? operates on a single 3.3 v power supply ? uses 5 v tolerant cells for vbus, cpu interface, and dma port input pins. ? supplied as a 100-pin qfp package * no radiation resistant design measure has been incorporated.
S1R72003 technical manual 2 epson rev.1.0 3. block diagram serial interface engine fifo sram utmi1.0 transceiver macro fifo controller suspend/resume controller dma endpoints endpoints endpoints endpoints packet handler transaction manager clock systhesis embedded usb front-end embedded 2.5kb sram ide or 8/16 bit ide like dma 60mhz test/debug module xint xwait xsleep xwr xrd xcs cd[7:0] ca[7:0] tin[1:0] tport[1:0] tsten atpgen scanen oscout clksel[1:0] xo xi ptest vc dm dp v bus xreset hdd[15:0] hda[2:0] xhcs1 xhcs0 xhior xhiow hdmarq xhdmack hiordy hintrq xhreset xhdasp xhpdiag
S1R72003 technical manual rev.1.0 epson 3 4. pin assignment v ss hiordy xhior xhiow hdmarq v dd hdd15 hdd0 hdd14 hdd1 hdd13 hdd2 hdd12 hdd3 v ss hdd11 hdd4 hdd10 hdd5 hdd9 hdd6 hdd8 hdd7 xhreset v dd 7 5 7 4 7 3 7 2 7 1 7 0 6 9 6 8 6 7 6 6 6 5 6 4 6 3 6 2 6 1 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 5 2 5 1 v dd 76 50 v ss x hdmack 77 49 oscout hintrq 78 48 v ss hda1 79 47 tin1 xhpdiag 80 46 tin0 hda0 81 45 tport1 hda2 82 44 tport0 xhcs0 83 43 scanen xhcs1 84 42 atpgen xhdasp 85 41 v dd v ss 86 40 cd7 clksel0 87 39 cd6 clksel1 88 38 cd5 nc 89 37 cd4 xv ss 90 36 v ss xv dd 91 35 cd3 nc 92 34 cd2 pv dd 93 33 cd1 nc 94 32 cd0 pv ss 95 31 xint vc 96 30 xwr ptest 97 29 xwait nc 98 28 xrd xi 99 27 xcs xo ## 26 v dd 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 r1 nc nc av dd av ss av dd av ss dp av ss dm av ss av dd tsten v bus xreset xsleep ca0 ca1 ca2 ca3 ca4 ca5 ca6 ca7 v ss epson S1R72003f00b100 top view
S1R72003 technical manual 4 epson rev.1.0 5. pin description 5.1 cpu interface symbol pin name pin no. type description cd7 cd6 cd5 cd4 cd3 cd2 cd1 cd0 cpu data 40 39 38 37 35 34 33 32 i/o (3 state pull up) cpu data bus during reads, register data is output from this bus. during writes, the cpu delivers the register data to be set through this bus. uses a 5v tolerant cell. ca7 ca6 ca5 ca4 ca3 ca2 ca1 ca0 cpu address 24 23 22 21 20 19 18 17 i (pull up) cpu address bus this bus specifies the register address. uses a 5v tolerant cell. xrd read strobe 28 i (pull up) cpu read strobe. uses a 5v tolerant cell. xwr write strobe 30 i (pull up) cpu write strobe. uses a 5v tolerant cell. xcs chip select 27 i (pull up) register select signal uses a 5v tolerant cell. xsleep sleep mode 16 i (pull up) sleep mode set signal. uses a 5v tolerant cell. when this pins is asserted during the snooze mode, the S1R72003f00b100 enters the sleep mode. the oscillation circuit halts during the sleep mode. you should be careful when the cpu uses oscout. the S1R72003f00b100 is roused from sleep mode in the following cases: when resume is asserted on the usb interface when the tport1 or tport0 signal changes states xint interrupt signal 31 o interrupt signal to the cpu. the initial value is hi-z/0. this can be set to 1 or 0. xwait wait signal 29 o wait signal to the cpu. the initial value is hi-z/0. this can be set to 1 or 0. oscout oscillator output 49 o cpu clock output. the frequency generated by the resonator connected to xi and xo pins is output from this pin.
S1R72003 technical manual rev.1.0 epson 5 5.2 ide/general-purpose port interface symbol pin name pin no. type description hdd15 hdd14 hdd13 hdd12 hdd11 hdd10 hdd9 hdd8 hdd7 hdd6 hdd5 hdd4 hdd3 hdd2 hdd1 hdd0 ide data/ universal data bus 69 67 65 63 60 58 56 54 53 55 57 59 62 64 66 68 i/o (3 state) ide data bus. uses a 5v tolerant cell. this bus also serves as a general-purpose port data bus, depending on the settings of the internal registers. if set to serve as a general-purpose port, the bus width can be set to 8 or 16 bits. hda2 hda1 hda0 ide register address 82 79 81 o ide register address signal. uses a 5v tolerant cell. if the general-purpose port function is selected, this signal is not used. xhcs1 control register select 84 o chip select for control register access if the general-purpose port function is selected, this signal is not used. xhcs0 command register select 83 o chip select for command block register access if the general-purpose port function is selected, this signal is not used. xhior ide read strobe 73 ide read strobe. uses a 5v tolerant cell. xhiow ide write strobe 72 o (ide mode/port master mode) i (port slave mode) ide write strobe. uses a 5v tolerant cell. during ide, this signal and xhior both serve as outputs. if the general-purpose port function is selected, this signal serves as output during master mode and serves as input during slave mode, depending on the settings of the internal registers. for detailed information on the signal timing, refer to the section, ?ac timing.? hintrq ide interrupt request 78 i ide interrupt request uses a 5v tolerant cell. if the general-purpose port function is selected, this signal is not used. hiordy i/o ready 74 i ide register ready signal uses a 5v tolerant cell. if the general-purpose port function is selected, this signal is not used. hdmarq dma request 71 i (ide mode/port master mode) o (port slave mode) dma transfer request uses a 5v tolerant cell. this signal serves as input during master mode and serves as output during slave mode depending on the settings of the internal registers. for detailed information on the signal timing, refer to the section, ?ac timing.?
S1R72003 technical manual 6 epson rev.1.0 symbol pin name pin no. type description xhdmack dma acknowledge 77 o (ide mode/port master mode) i (port slave mode) dma transfer acknowledge uses a 5v tolerant cell. this signal serves as output during master mode and serves as input during slave mode depending on the settings of the internal registers. for detailed information on the signal timing, refer to the section, ?ac timing.? xhpdiag passed diagnostics 80 i diagnostic sequence-finished signal uses a 5v tolerant cell. xhdasp drive active/ slave present 85 i drive active/slave drive present uses a 5v tolerant cell. xhreset ide reset 52 o ide bus reset 5.3 usb interface symbol pin name pin no. type description dp usb positive signal 8 i/o usb data line, data+ dm usb negative signal 10 i/o usb data line, data- v bus usb bus detect signal 14 i usb bus detect signal. uses a 5v tolerant cell. r1 internal operation set pin 1 i/o internal operation set pin connect a 6.2 k ? 1% resistor between this pin and avss (pin 5). this resistor must be connected as close as possible to pins 1 and 5. xi resonator input 99 i xo resonator output 100 o xi is an input for the internal oscillator circuit or input from an external oscillator. xo is an output for the internal oscillator circuit. leave these pins open when using a crystal oscillator. vc pllvco 96 i internal test pin. during normal use, connect this pin to gnd. ptest pll test 97 i internal test pin. during normal use, connect this pin to gnd. 5.4 system blocks and others symbol pin name pin no. type description xreset chip reset 15 i chip reset. uses a 5v tolerant cell. clksel1 88 i clksel0 oscillator clock select 87 i oscillation frequency select clksel1 clksel0 frequency of the connected resonator low low 12 mhz low high 16 mhz high low 20 mhz high high 24 mhz nc no connection 2, 3, 89, 92, 94, 98 - these pins are not connected internally.
S1R72003 technical manual rev.1.0 epson 7 5.5 test signals symbol pin name pin no. type description tin1 tin0 test mode 47 46 i (pull down) mode set input pin 00: normal others: internal test mode tport1 tport0 test port i/o 45 44 i/o general-purpose input/output port for debugging tsten internal test mode 13 i (pull down) internal pulldown. during normal use, connect this pin low. atpgen internal test mode 42 i (pull down) test input pin. during normal use, connect this pin low. scanen internal test mode 43 i (pull down) test input pin. during normal use, connect this pin low. 5.6 power supply and gnd symbol pin name pin no. type description v dd power supply for logic part 26, 41, 51, 70, 76 p 3.3v power supply pin for the logic block v ss ground for logic part 25, 36, 48, 50, 61, 75, 86 p ground pin for the logic block xv dd power supply for logic part in utmi 91 p 3.3v power supply pin for the transceiver macro unit logic block xv ss ground for logic part in utmi 90 p ground pin for the transceiver macro unit logic block pv dd power supply for pll part in utmi 93 p 3.3v power supply pin for the transceiver macro unit pll pv ss ground for pll part in utmi 95 p ground pin for the transceiver macro unit pll av dd power supply for analog part in utmi 4, 6, 12 p 3.3v power supply pin for the transceiver macro unit analog block av ss ground for analog part in utmi 5, 7, 9, 11 p ground pin for the transceiver macro unit analog block.
S1R72003 technical manual 8 epson rev.1.0 6. functional description the function of each block of the S1R72003f00b100 is described below. 6.1 utmi1.0 transceiver macro this is a utmi1.0-compliant usb 2.0 transceiver macro. it supports hs mode (480 mbps) and fs mode (12 mbps). the transceiver macro contains an analog hs/fs driver, receiver, and terminator to provide a usb interface. it also contains an oscillator circuit which generates a 480 mhz clock required for hs transfer and a 60 mhz clock required for the operation of the internal logic. this oscillator circuit accepts as its input clock a 12, 16, 20, or 24 mhz crystal resonator. the transceiver macro uses an 8-bit parallel interface for interface with the sie. the transceiver macro processes the communication bit stream by nrzi encoding/decoding. it also has an internal data handler that adds sync, eop, and bit stuff to the transmit data. when receiving data, it detects/removes sync and eop and removes the bit stuff. the transceiver macro incorporates the elasticity buffer to counter data underruns/overruns caused by frequency deviations on the data transmit/receive sides in the hs mode, and a squelch circuit to discriminate between serial data and noise. for more information, refer to the utmi 1.0 specifications. 6.2 serial interface engine 6.2.1 packet handler this unit processes the packet (by dissolving it into the various fields: pid, addr, data, crc, endpoint number, and frame number). it also checks and generates crc. 6.2.2 transaction manager this unit manages transactions such as usb address verification and handshake verification/creation. 6.2.3 endpoints the serial interface incorporates endpoint 0 (in/out) and three general-purpose endpoints (epa, epb, and epc). the in/out direction, maximum packet size, and transfer type (bulk, interrupt, or isochronous) of the general-purpose endpoints can be individually set using an internal register. (isochronous transfer is supported only by epc.) 6.2.4 suspend/resume controller this unit controls suspend and resume. 6.3 fifo sram this buffer is used to accommodate the endpoints (2.5 kb). it is user programmable, but total 128 bytes comprised of 64 bytes for endpoint and 64 bytes for cbw/csw are reserved area. the fifo sram reserves a space for maxpacketsize (twice the size with the doublebuf setting) according to each endpoint setting. the amount of space the fifo sram reserves must not exceed 2.5 kb. 6.4 fifo controller this unit manages the fifo sram address (user programmable), generates timing signals, and arbitrates bus contention. 6.5 dma the dma in the S1R72003f00b100 supports general-purpose dma ports and ide interface. the general-purpose dma ports accommodate both master and slave operations. the bus width can be switched to 8 or 16 bits. the dma can function as the ide master, and supports pio modes 0/1/2/3/4, multiword dma modes 0/1/2, and ultra-dma modes 0/1/2/3/4. 6.6 test/debug module the operation mode (test mode) of this module is switched by an input signal.
S1R72003 technical manual rev.1.0 epson 9 7. register 7.1 register map indicates the register or bit that can be read and/or written even if the controller is in the snooze mode. address register name reset bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x00 mainintstat 0x00 sieintstat bulkintstat eprintstat ideintstat portintstat rcvep0setup 0x01 sieintstat 0x00 vbuschanged non_j detectreset detectsuspend rcvsof chirpcmp restorecmp 0x02 bulkintstat 0x00 cbwcmp cbwshort cbwlong cbwerr cswcmp cswerr bulkincmp bulkoutcmp 0x03 eprintstat 0x00 ep0intstat epaintstat epbintstat epcintstat 0x04 ideintstat 0x00 dtcmp detectintrq detectterm 0x05 (reserved) 0xxx 0x06 portintstat 0x00 portint1 portint0 0x07 (reserved) 0xxx 0x08 ep0intstat 0x00 pingtranack intranack outtranack intrannak outtrannak intranerr outtranerr 0x09 epaintstat 0x00 pingtranack outshortack intranack outtranack intrannak outtrannak intranerr outtranerr 0x0a epbintstat 0x00 pingtranack outshortack intranack outtranack intrannak outtrannak intranerr outtranerr 0x0b epcintstat 0x00 pingtranack outshortack intranack outtranack intrannak outtrannak intranerr outtranerr 0x0c (reserved) 0xxx 0x0d (reserved) 0xxx 0x0e (reserved) 0xxx 0x0f (reserved) 0xxx 0x10 mainintenb 0x00 ensieintstat enbulkintstat eneprintstat enideintstat enportintstat enrcvep0 setup 0x11 sieintenb 0x00 envbus changed ennon_j endetectreset endetect suspend enrcvsof enchirpcmp enrestorecmp 0x12 bulkintenb 0x00 encbwcmp encbwshort encbwlong encbwerr encswcmp encswerr enbulkincmp enbulkout cmp 0x13 eprintenb 0x00 enep0intstat enepaintstat enepbintstat enepcintstat 0x14 ideintenb 0x00 endtcmp endetectintrq endetectterm 0x15 (reserved) 0xxx 0x16 portintenb 0x00 enportint1 enportint0 0x17 (reserved) 0xxx 0x18 ep0intenb 0x00 enpingtran ack enintranack enouttran ack enintrannak enouttran nak enintranerr enouttranerr 0x19 epaintenb 0x00 enpingtran ack enoutshort ack enintranack enouttran ack enintrannak enouttran nak enintranerr enouttranerr 0x1a epbintenb 0x00 enpingtran ack enoutshort ack enintranack enouttran ack enintrannak enouttran nak enintranerr enouttranerr 0x1b epcintenb 0x00 enpingtran ack enoutshort ack enintranack enouttran ack enintrannak enouttran nak enintranerr enouttranerr 0x1c (reserved) 0xxx 0x1d (reserved) 0xxx 0x1e (reserved) 0xxx 0x1f (reserved) 0xxx
S1R72003 technical manual 10 epson rev.1.0 address register name reset bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x20 chipreset 0x00 resetsie resetall 0x21 revisionnum 0x31 0x22 pmcontorol 0x00 insnooze resetutm pllsel analog pwdown snooze 0x23 usbcontrol 0x00 disbusdetect sendwakeup restoreusb gochirp activeusb 0x24 usbstatus 0xxx vbus fsxhs linestate[1:0] 0x25 xcvrcontrol 0x41 termselect xcvrselect opmode[1:0] 0x26 usbtest 0x00 enhstest se0_nak test_j test_k testpacket 0x27 (reserved) 0xxx 0x28 usbaddress 0x00 usbaddress[6:0] 0x29 eprcontrol 0x00 dmarunning allfifoclr autoenshort allforcenak eprforce stall 0x2a bulkonlycontrol 0x00 gocbwmode gocswmode cswsel 0x2b bulkonlyconfig 0x00 cbwepnumber cswepnumber 0x2c (reserved) 0xxx 0x2d (reserved) 0xxx 0x2e (reserved) 0xxx 0x2f 0x00 rdyxwait waitmode intmode 0x30 ep0setup_0 0x00 0x31 ep0setup_1 0x00 0x32 ep0setup_2 0x00 0x33 ep0setup_3 0x00 0x34 ep0setup_4 0x00 0x35 ep0setup_5 0x00 0x36 ep0setup_6 0x00 0x37 ep0setup_7 0x00 0x38 framenumber_h 0x80 fninvalid framenumber[10:8] 0x39 framenumber_l 0x00 framenumber[7:0] 0x3a (reserved) 0xxx 0x3b (reserved) 0xxx 0x3c (reserved) 0xxx 0x3d (reserved) 0xxx 0x3e (reserved) 0xxx 0x3f (reserved) 0xxx 0x40 ep0config_0 0x00 inxout 0x41 (reserved) 0xxx 0x42 ep0control_0 0x00 autoforcenak inenshortpkt inforcenak inforcestall outforcenak outforce stall 0x43 ep0control_1 0x00 intogglestat intoggleset intoggleclr outtogglestat outtoggleset outtoggleclr 0x44 (reserved) 0xxx 0x45 ep0fiforemain 0x00 ep0fiforemain counter[6:0] 0x46 ep0fifoforcpu 0xxx ep0fifodata 0x47 ep0fifocontrol 0x80 fifoempty fifofull fifoclr enfifowr enfiford 0x48 (reserved) 0xxx 0x49 (reserved) 0xxx 0x4a (reserved) 0xxx 0x4b (reserved) 0xxx 0x4c (reserved) 0xxx 0x4d (reserved) 0xxx 0x4e (reserved) 0xxx 0x4f (reserved) 0xxx
S1R72003 technical manual rev.1.0 epson 11 address register name reset bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit0 0x50 epaconfig_0 0x00 inxout endpointnumber[3:0] 0x51 epaconfig_1 0x00 joinide togglemode enendpoint doublebuf maxpacketsize[2:0] 0x52 epacontrol_0 0x00 autoforcenak enshortpkt autoforcenak short forcenak forcestall 0x53 epacontrol_1 0x00 togglestat toggleset toggleclr 0x54 epafiforemain_h 0x00 epafiforemain counter[15:8] 0x55 epafiforemain_l 0x00 epafiforemain c ounter[7:0] 0x56 epafifoforcpu 0xxx epafifodata 0x57 epafifocontrol 0x80 fifoempty fifofull fifoclr enfifowr enfiford 0x58 epbconfig_0 0x00 inxout endpointnumber[3:0] 0x59 epbconfig_1 0x00 joinide togglemode enendpoint doublebuf maxpacketsize[2:0] 0x5a epbcontrol_0 0x00 autoforcenak enshortpkt autoforcenak short forcenak forcestall 0x5b epbcontrol_1 0x00 togglestat toggleset toggleclr 0x5c epbfiforemain_h 0x00 epbfiforemain counter[15:8] 0x5d epbfiforemain_l 0x00 epbfiforemain c ounter[7:0] 0x5e epbfifoforcpu 0xxx epbfifodata 0x5f epbfifocontrol 0x80 fifoempty fifofull fifoclr enfifowr enfiford 0x60 epcconfig_0 0x00 inxout iso endpointnumber[3:0] 0x61 epcconfig_1 0x00 joinide togglemode enendpoint doublebuf maxpacketsize[2:0] 0x62 epccontrol_0 0x00 autoforcenak enshortpkt autoforcenak short forcenak forcestall 0x63 epccontrol_1 0x00 togglestat toggleset toggleclr 0x64 epcfiforemain_h 0x00 epcfiforemain counter[15:8] 0x65 epcfiforemain_l 0x00 epcfiforemain counter[7:0] 0x66 epcfifoforcpu 0xxx epcfifodata 0x67 epcfifocontrol 0x80 fifoempty fifofull fifoclr enfifowr enfiford 0x68 isomaxsize_h 0x00 isomaxpacketsize[10:8] 0x69 isomaxsize_l 0x00 isomaxpacketsize[7:2] 0x6a (reserved) 0xxx 0x6b (reserved) 0xxx 0x6c (reserved) 0xxx 0x6d (reserved) 0xxx 0x6e (reserved) 0xxx 0x6f (reserved) 0xxx 0x70 (reserved) 0xxx 0x71 (reserved) 0xxx 0x72 (reserved) 0xxx 0x73 (reserved) 0xxx 0x74 (reserved) 0xxx 0x75 (reserved) 0xxx 0x76 (reserved) 0xxx 0x77 (reserved) 0xxx 0x78 (reserved) 0xxx 0x79 (reserved) 0xxx 0x7a (reserved) 0xxx 0x7b (reserved) 0xxx 0x7c (reserved) 0xxx 0x7d (reserved) 0xxx 0x7e (reserved) 0xxx 0x7f (reserved) 0xxx
S1R72003 technical manual 12 epson rev.1.0 address register name reset bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit0 0x80 ide_status 0xxx dmarq dmack intrq iordy pdiag dasp 0x81 ide_config_0 0x00 idebusreset notide ultra dma 0x82 ide_config_1 0x00 activeide delaystrobe slave interlock pdreqlevel swap bus8 0x83 (reserved) 0xxx 0x84 ide_rmod 0x00 registerassertpulsewidth[3:0] registernegatepulsewidth[3:0] 0x85 ide_tmod 0x00 transferassertpulsewidth[3:0] transfernegatepulsewidth[3:0] 0x86 ide_umod 0x00 ultradmacycle[3:0] 0x87 (reserved) 0xxx 0x88 ide_control_0 0x00 ideflush idefclr dtgo 0x89 (reserved) 0xxx 0x8a ide_count_h 0x00 count[23:16] 0x8b ide_count_m 0x00 count[15:8] 0x8c ide_count_l 0x00 count[7:0] 0x8d ide_crccontrol 0x00 clear 0x8e ide_crc_h 0x4a crc[15:8] 0x8f ide_crc_l 0xba crc[7:0] 0x90 ide_cs00 0xxx 0x91 ide_cs01 0xxx 0x92 ide_cs02 0xxx 0x93 ide_cs03 0xxx 0x94 ide_cs04 0xxx 0x95 ide_cs05 0xxx 0x96 ide_cs06 0xxx 0x97 ide_cs07 0xxx 0x98 ide_cs10 0xxx 0x99 ide_cs11 0xxx 0x9a ide_cs12 0xxx 0x9b ide_cs13 0xxx 0x9c ide_cs14 0xxx 0x9d ide_cs15 0xxx 0x9e ide_cs16 0xxx 0x9f ide_cs17 0xxx 0xa0 cbw_00 0xxx 0xa1 cbw_01 0xxx 0xa2 cbw_02 0xxx 0xa3 cbw_03 0xxx 0xa4 cbw_04 0xxx 0xa5 cbw_05 0xxx 0xa6 cbw_06 0xxx 0xa7 cbw_07 0xxx 0xa8 cbw_08 0xxx 0xa9 cbw_09 0xxx 0xaa cbw_10 0xxx 0xab cbw_11 0xxx 0xac cbw_12 0xxx 0xad cbw_13 0xxx 0xae cbw_14 0xxx 0xaf cbw_15 0xxx
S1R72003 technical manual rev.1.0 epson 13 address register name reset bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit0 0xb0 cbw_16 0xxx 0xb1 cbw_17 0xxx 0xb2 cbw_18 0xxx 0xb3 cbw_19 0xxx 0xb4 cbw_20 0xxx 0xb5 cbw_21 0xxx 0xb6 cbw_22 0xxx 0xb7 cbw_23 0xxx 0xb8 cbw_24 0xxx 0xb9 cbw_25 0xxx 0xba cbw_26 0xxx 0xbb cbw_27 0xxx 0xbc cbw_28 0xxx 0xbd cbw_29 0xxx 0xbe cbw_30 0xxx 0xbf (reserved) 0xxx 0xc0 csw0_00 0xxx 0xc1 csw0_01 0xxx 0xc2 csw0_02 0xxx 0xc3 csw0_03 0xxx 0xc4 csw0_04 0xxx 0xc5 csw0_05 0xxx 0xc6 csw0_06 0xxx 0xc7 csw0_07 0xxx 0xc8 csw0_08 0xxx 0xc9 csw0_09 0xxx 0xca csw0_10 0xxx 0xcb csw0_11 0xxx 0xcc csw0_12 0xxx 0xcd (reserved) 0xxx 0xce (reserved) 0xxx 0xcf (reserved) 0xxx 0xd0 csw1_00 0xxx 0xd1 csw1_01 0xxx 0xd2 csw1_02 0xxx 0xd3 csw1_03 0xxx 0xd4 csw1_04 0xxx 0xd5 csw1_05 0xxx 0xd6 csw1_06 0xxx 0xd7 csw1_07 0xxx 0xd8 csw1_08 0xxx 0xd9 csw1_09 0xxx 0xda csw1_10 0xxx 0xdb csw1_11 0xxx 0xdc csw1_12 0xxx 0xdd (reserved) 0xxx 0xde (reserved) 0xxx 0xdf (reserved) 0xxx
S1R72003 technical manual 14 epson rev.1.0 address register name reset bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit0 0xe0 portdir 0x00 portdir1 portdir0 0xe1 portdata 0xxx portdata1 portdata0 0xe2 (reserved) 0xxx 0xe3 (reserved) 0xxx 0xe4 (reserved) 0xxx 0xe5 (reserved) 0xxx 0xe6 (reserved) 0xxx 0xe7 (reserved) 0xxx 0xe8 (reserved) 0xxx 0xe9 (reserved) 0xxx 0xea (reserved) 0xxx 0xeb (reserved) 0xxx 0xec (reserved) 0xxx 0xed (reserved) 0xxx 0xee (reserved) 0xxx 0xef (reserved) 0xxx 0xf0 (reserved) 0xxx 0xf1 (reserved) 0xxx 0xf2 (reserved) 0xxx 0xf3 (reserved) 0xxx 0xf4 (reserved) 0xxx 0xf5 (reserved) 0xxx 0xf6 (reserved) 0xxx 0xf7 (reserved) 0xxx 0xf8 (reserved) 0xxx 0xf9 (reserved) 0xxx 0xfa (reserved) 0xxx 0xfb (reserved) 0xxx 0xfc (reserved) 0xxx 0xfd (reserved) 0xxx 0xfe (reserved) 0xxx 0xff (reserved) 0xxx * access to reserved registers is prohibited.
S1R72003 technical manual rev.1.0 epson 15 7.2 register details 7.2.1 00h main interrupt status (mainintstat) address register name r/w bit symbol d escription reset 00h mainintstat r 7: sieintstat 0: none 1: sie interrupt occurred r 6: bulkintstat 0: none 1: bulk interrupt occurred r 5: eprintstat 0: none 1: epr interrupt occurred r 4: ideintstat 0: none 1: ide interrupt occurred 3: 0: 1: r 2: portintstat 0: none 1: port interrupt occurred 1: 0: 1: r (w) 0: rcvep0setup 0: none 1: receive ep0 setup transaction 00h when an interrupt to the cpu is generated by the S1R72003f00b100, the cpu reads this register during interrupt handling to determine the cause of the interrupt. for bits that indirectly indicate the cause of the interrupt, the cpu reads the interrup t status register corresponding to one of the bits to determine the cause of the interrupt. if all interrupt causes in that interrupt s tatus register are cleared, the corresponding bit in this register is automatically cleared. for bits that directly indicate the cause of the interrupt, it is possible to clear the cause of the interrupt by writing 1 to the corresponding bit. if any bit in the mainintenb register is enabled for interrupt and the corresponding interrupt cause in this register is set to 1, the xint pin is asserted to generate an interrupt to the cpu. when all of the corresponding interrupt causes are cleared, the xint pin is negated. bit 7 sieintstat indirectly indicates the cause of the interrupt. this bit is set to 1 when the cause of the interrupt exists in the sieintstat register and the corresponding sieintenb register bit is enabled. this bit is effective even during snooze. bit 6 bulkintstat indirectly indicates the cause of the interrupt. this bit is set to 1 when the cause of the interrupt exists in the bulkintsta t register and the corresponding bulkintenb register bit is enabled. bit 5 eprintstat indirectly indicates the cause of the interrupt. this bit is set to 1 when the cause of the interrupt exists in the eprintstat register and the corresponding eprintenb register bit is enabled. bit 4 ideintstat indirectly indicates the cause of the interrupt. this bit is set to 1 when the cause of the interrupt exists in the ideintstat register and the corresponding ideintenb register bit is enabled. bit 3 reserved bit 2 portintstat indirectly indicates the cause of the interrupt. this bit is set to 1 when the cause of the interrupt exists in the portintsta t register and the corresponding portintenb register bit is enabled. this bit is effective even during snooze. bit 1 reserved bit 0 rcvep0setup directly indicates the cause of the interrupt. this bit is set to 1 if the received data is stored in registers ep0set up_0 through ep0setup_7 after the setup stage at endpoint 0 is completed. at the same time, in the ep0control_0 register, the inforcestall and outforcestall bits are automatically set to 0 and the inforcenak and outforcenak bits are set to 1. the status of the inforcenak, outforcenak, inforcestall and outforcestall bits in the ep0control_0 cannot be changed when the rcvep0setup bit is 1.
S1R72003 technical manual 16 epson rev.1.0 7.2.2 01h sie interrupt status (sieintstat) address register name r/w bit symbol d escription reset 01h sieintstat r (w) 7: vbuschanged 0: none 1: vbus changed r (w) 6: non_j 0: none 1: non j interrupt occurred r (w) 5: detectreset 0: none 1: usb reset detected r (w) 4: detectsuspend 0: none 1: usb suspend detected r (w) 3: rcvsof 0: none 1: received sof token r (w) 2: chirpcmp 0: none 1: chirp complete r (w) 1: restorecmp 0: none 1: restore complete 0: 0: 1: 00h this register shows sie-related interrupts. the bits in this register directly indicate the cause of the interrupt. when a bi t in this register is set to 1, writing a 1 to the bit can clear the cause of the interrupt. bit 7 vbuschanged this bit is set to 1 when the vbus pin status changes. you can check the vbus status with the vbus bit in the usbstatus register. if this bit is set to 1 during gochirp or restoreusb processing and the vbus bit is 0, the cable is disconnected. clear the gochirp and restoreusb bits to 0 to abort the current processing. this bit is effective even during snooze. bit 6 non_j this bit is set to 1 when a state other than j is detected on the usb bus during snooze. the state (se0 or k) can be determined by inspecting the usbstatus register linestate bit. according to the state identified, remove the S1R72003f00b100 from the snooze state, then perform gochirp or restoreusb processing. this bit is effective only during snooze. bit 5 detectreset this bit is set to 1 when the usb reset state is detected. when the usb is operating in the hs operation mode, it enters the fs operation mode for detecting a usb reset state. when this bit is set to 1, set the usbcontrol register disbusdetect bit to 1 to disable usb reset/suspend state detection. the disbusdetect bit should be cleared to 0 to enable usb reset/suspend state detection after the reset processing is completed. hs detection handshake can be initiated using the usbcontrol register gochirp bit. the usb reset detection is effective when the usbcontrol register activeusb bit is set to 1. bit 4 detectsuspend this bit is set to 1 when the usb suspend state is detected. when the usb is operating in the hs operation mode, it enters the fs operation mode for detecting a usb reset state. after the usb suspend state is detected, the pll oscillation in the S1R72003f00b100 can be halted (set to the snooze mode) by setting the pmcontrol register snooze bit to 1. bit 3 rcvsof this bit is set to 1 when an sof token is received. bit 2 chirpcmp this bit is set to 1 when hs detection handshake initiated by the usbcontrol register gochirp bit finishes. following this interrupt, the current usb operation mode (fs or hs) can be determined by reading the usbstatus register fsxhs bit. bits 1 restorecmp this bit is set to 1 when the resume processing initiated by the usbcontrol register restoreusb bit finishes. when this bit is set to 1, the usb returns to its operation mode (fs or hs) before being suspended. bits 0 reserved
S1R72003 technical manual rev.1.0 epson 17 7.2.3 02h bulk interrupt status (bulkintstat) address register name r/w bit symbol d escription reset 02h bulkintstat r (w) 7: cbwcmp 0: none 1: cbw packet received r (w) 6: cbwshort 0: none 1:cbwshortpacketreceived r (w) 5: cbwlong 0: none 1:cbw longpacketreceived r (w) 4: cbwerr 0: none 1: cbw error r (w) 3: cswcmp 0: none 1: csw transfer complete r (w) 2: cswerr 0: none 1: csw error r (w) 1: bulkincmp 0: none 1: bulk in transfer complete r (w) 0: bulkoutcmp 0: none 1:bulkouttransfer complete 00h this register shows the bulk transfer related interrupts. the cbwcmp, cbwshort, cbwlong, cbwerr, cswcmp, and cswerr bits are used in the usb storage-class bulkonly transport protocol. when a bit in this register is set to 1, writing a 1 to th e bit can clear the cause of the interrupt. bit 7 cbwcmp this bit is set to 1 if while the bulkonlycontrol register gocbwmode bit = 1, 31 bytes long data is received normally at the endpoint set in the bulkonlyconfig register cbwepnumber. bit 6 cbwshort this bit is set to 1 if while the bulkonlycontrol register gocbwmode bit = 1, data of less than 31 bytes in length is received at the e ndpoint set in the bulkonlyconfig register cbwepnumber. bit 5 cbwlong this bit is set to 1 if while the bulkonlycontrol register gocbwmode bit = 1, data of more than 31 bytes in length is received at the e ndpoint set in the bulkonlyconfig register cbwepnumber. bit 4 cbwerr when the bulkonlycontrol register gocbwmode bit is 1, this bit is set to 1 if a transaction error occurred at an endpoint set in the bulkonlyconfig register cbwepnumber bits. bit 3 cswcmp when the bulkonlycontrol register gocswmode bit is 1, this bit is set to 1 if an in transaction is executed at an endpoint set in the bulkonlyconfig register cswepnumber bits and the S1R72003f00b100 receives an ack from the host in response to the data on registers csw0_00 through csw0_12 or csw1_00 through csw1_12 sent to the host. bit 2 cswerr when the bulkonlycontrol register gocswmode bit is 1, this bit is set to 1 if an in transaction is executed at an endpoint set in the bulkonlyconfig register cswepnumber bits and the S1R72003f00b100 receives no ack from the host in response to the data on registers csw0_00 through csw0_12 or csw1_00 through csw1_12 sent to the host. bit 1 bulkincmp this bit is set to 1 when the dma transfer for the number of bytes specified as the dma transfer size completes in an in transaction at an endpoint where the ep[a,b,c]config_1 register joinide bit is 1, completing the transfer of all data in the fifo. the time at which this interrupt is generated depends on the eprcontrol register autoenshort bit. for more information, refer to the description of the eprcontrol register autoenshort bit. bit 0 bulkoutcmp this bit is set to 1 together with the dtcmp bit when the dma transfer for the number of bytes specified as the dma transfer size completes in an out transaction at an endpoint where the ep[a,b,c]config_1 register joinide bit is 1.
S1R72003 technical manual 18 epson rev.1.0 7.2.4 03h epr interrupt status (eprintstat) address register name r/w bit symbol d escription reset 03h eprintstat 7: 0: 1: 6: 0: 1: 5: 0: 1: 4: 0: 1: r 3: ep0intstat 0: none 1: ep0 interrupt occurred r 2: epaintstat 0: none 1: epa interrupt occurred r 1: epbintstat 0: none 1: epb interrupt occurred r 0: epcintstat 0: none 1: epc interrupt occurred 00h this register indirectly indicates the cause of the interrupt for each e ndpoint. when all the enabled interrupt causes (root causes) at an endpoint indicated by a bit are cleared, that bit is cleared. bit 7 reserved bit 6 reserved bit 5 reserved bit 4 reserved bit 3 ep0intstat this bit is set to 1 when the cause of the interrupt exists in the ep0intstat register, and the bit in the ep0intenb register corresponding to that cause of the interrupt is enabled for interrupt. bit 2 epaintstat this bit is set to 1 when the cause of the interrupt exists in the epaintstat register, and the bit in the epaintenb register corresponding to that cause of the interrupt is enabled for interrupt. bit 1 epbintstat this bit is set to 1 when the cause of the interrupt exists in the epbintstat register, and the bit in the epbintenb register corresponding to that cause of the interrupt is enabled for interrupt. bit 0 epcintstat this bit is set to 1 when the cause of the interrupt exists in the epcintstat register, and the bit in the epcintenb register corresponding to that cause of the interrupt is enabled for interrupt.
S1R72003 technical manual rev.1.0 epson 19 7.2.5 04h ide interrupt status (ideintstat) address register name r/w bit symbol d escription reset 04h ideintstat 7: 0: 1: 6: 0: 1: 5: 0: 1: 4: 0: 1: 3: 0: 1: r (w) 2: dtcmp 0: none 1: dma transfer complete r (w) 1: detectintrq 0: none 1: intrq detected r (w) 0: detectterm 0: none 1: terminate detected 00h this register shows the interrupts from the ide interface. the bits in this register directly indicate the cause of the interr upt. when a bit in this register is set to 1, writing a 1 to the bit can clear the cause of the interrupt. bit 7 reserved bit 6 reserved bit 5 reserved bit 4 reserved bit 3 reserved bit 2 dtcmp this bit is set to 1 when the dma transfer activated by the ide_control_0 register dtgo bit finishes by transferring as many bytes as specified by the dma transfer size. also, this bit is set to 1 when the dma transfer is forcibly terminated by writing a 0 to the ide_control_0 register dtgo bit. bit 1 detectintrq this bit is set to 1 when the leading edge of the hintrq signal on the ide interface is detected. bit 0 detectterm this bit is set to 1 simultaneously with the dtcmp bit and the transfer is aborted if the device negates hdmarq during ultra dma transfer in ide. 7.2.6 05h reserved address register name r/w bit symbol description reset 05h (reserved) 7: 0: 1: 6: 0: 1: 5: 0: 1: 4: 0: 1: 3: 0: 1: 2: 0: 1: 1: 0: 1: 0: 0: 1: 00h
S1R72003 technical manual 20 epson rev.1.0 7.2.7 06h port interrupt status (portintstat) address register name r/w bit symbol d escription reset 06h portintstat 7: 0: 1: 6: 0: 1: 5: 0: 1: 4: 0: 1: 3: 0: 1: 2: 0: 1: r (w) 1: portint1 0: none 1:port1input signal changed r (w) 0: portint0 0: none 1:port0input signal changed 00h this register shows general-purpose io port interrupts. the bits in this register directly indicate the cause of the interrupt . when a bit in this register is set to 1, writing a 1 to the bit can clear the cause of the interrupt. bit 7 reserved bit 6 reserved bit 5 reserved bit 4 reserved bit 3 reserved bit 2 reserved bit 1 portint1 this bit is set to 1 if while port1 is set for input, the input signal on port1 changes state. this bit is effective even during snooze. bit 0 portint0 this bit is set to 1 if while port0 is set for input, the input signal on port0 changes state. this bit is effective even during snooze. 7.2.8 07h reserved address register name r/w bit symbol description reset 07h (reserved) 7: 0: 1: 6: 0: 1: 5: 0: 1: 4: 0: 1: 3: 0: 1: 2: 0: 1: 1: 0: 1: 0: 0: 1: 00h
S1R72003 technical manual rev.1.0 epson 21 7.2.9 08h ep0 interrupt status (ep0intstat) address register name r/w bit symbol d escription reset 08h ep0intstat r (w) 7: pingtranack 0: none 1: ping transaction ack 6: 0: none 1: r (w) 5: intranack 0: none 1: in transaction ack r (w) 4: outtranack 0: none 1: out transaction ack r (w) 3: intrannak 0: none 1: in transaction nak r (w) 2: outtrannak 0: none 1: out transaction nak r (w) 1: intranerr 0: none 1: in transaction error r (w) 0: outtranerr 0: none 1: out transaction error 00h this register shows the endpoint 0 interrupt status. the bits in this register directly indicate the cause of the interrupt. when a bit in this register is set to 1, writing a 1 to the bit can clear the cause of the interrupt. bit 7 pingtranack this bit is set to 1 when an ack is returned to the host in a ping transaction. bit 6 reserved bit 5 intranack this bit is set to 1 when an ack is received from the host in an in transaction. bit 4 outtranack this bit is set to 1 when an ack is returned to the host in an out transaction. bit 3 intrannak this bit is set to 1 when an nak is returned to the host in an in transaction. bit 2 outtrannak this bit is set to 1 when an nak is returned to the host for an out or ping transaction. bit 1 intranerr this bit is set to 1 when either a stall is returned to the host, a packet error occurs or a handshake times out in an in transaction. bit 0 outtranerr this bit is set to 1 when a stall is returned to the host or a packet error is found in an out transaction.
S1R72003 technical manual 22 epson rev.1.0 7.2.10 09h epa interrupt status (epaintstat) address register name r/w bit symbol d escription reset 09h epaintstat r (w) 7: pingtranack 0: none 1: ping transaction ack r (w) 6: outshortack 0: none 1: out short packet ack r (w) 5: intranack 0: none 1: in transaction ack r (w) 4: outtranack 0: none 1: out transaction ack r (w) 3: intrannak 0: none 1: in transaction nak r (w) 2: outtrannak 0: none 1: out transaction nak r (w) 1: intranerr 0: none 1: in transaction error r (w) 0: outtranerr 0: none 1: out transaction error 00h this register shows the endpoint a interrupt status. the bits in this register directly indicate the cause of the interrupt. when a bit in this register is set to 1, writing a 1 to the bit can clear the cause of the interrupt. bit 7 pingtranack this bit is set to 1 when an ack is returned to the host in a ping transaction. bit 6 outshortack this bit is set to 1 together with the outtranack bit when a short packet is received and an ack is returned in an out transaction. bit 5 intranack this bit is set to 1 when an ack is received from the host in an in transaction. bit 4 outtranack this bit is set to 1 when an ack is returned to the host in an out transaction. bit 3 intrannak this bit is set to 1 when an nak is returned to the host in an in transaction. bit 2 outtrannak this bit is set to 1 when an nak is returned to the host for an out or ping transaction. bit 1 intranerr this bit is set to 1 when either a stall is returned to the host, a packet error occurs or a handshake times out in an in transaction. bit 0 outtranerr this bit is set to 1 when a stall is returned to the host or a packet error is found in an out transaction.
S1R72003 technical manual rev.1.0 epson 23 7.2.11 0ah epb interrupt status (epbintstat) address register name r/w bit symbol description reset 0ah epbintstat r (w) 7: pingtranack 0: none 1: ping transaction ack r (w) 6: outshortack 0: none 1: out short packet ack r (w) 5: intranack 0: none 1: in transaction ack r (w) 4: outtranack 0: none 1: out transaction ack r (w) 3: intrannak 0: none 1: in transaction nak r (w) 2: outtrannak 0: none 1: out transaction nak r (w) 1: intranerr 0: none 1: in transaction error r (w) 0: outtranerr 0: none 1: out transaction error 00h this register shows the endpoint b interrupt status. the bits in this register directly indicate the cause of the interrupt. when a bit in this register is set to 1, writing a 1 to the bit can clear the cause of the interrupt. bit 7 pingtranack this bit is set to 1 when an ack is returned to the host in a ping transaction. bit 6 outshortack this bit is set to 1 together with the outtranack bit when a short packet is received and an ack is returned in an out transaction. bit 5 intranack this bit is set to 1 when an ack is received from the host in an in transaction. bit 4 outtranack this bit is set to 1 when an ack is returned to the host in an out transaction. bit 3 intrannak this bit is set to 1 when an nak is returned to the host in an in transaction. bit 2 outtrannak this bit is set to 1 when an nak is returned to the host for an out or ping transaction. bit 1 intranerr this bit is set to 1 when either a stall is returned to the host, a packet error occurs or a handshake times out in an in transaction. bit 0 outtranerr this bit is set to 1 when a stall is returned to the host or a packet error is found in an out transaction.
S1R72003 technical manual 24 epson rev.1.0 7.2.12 0bh epc interrupt status (epcintstat) address register name r/w bit symbol d escription reset 0bh epcintstat r (w) 7: pingtranack 0: none 1: ping transaction ack r (w) 6: outshortack 0: none 1: out short packet ack r (w) 5: intranack 0: none 1: in transaction ack r (w) 4: outtranack 0: none 1: out transaction ack r (w) 3: intrannak 0: none 1: in transaction nak r (w) 2: outtrannak 0: none 1: out transaction nak r (w) 1: intranerr 0: none 1: in transaction error r (w) 0: outtranerr 0: none 1: out transaction error 00h this register shows the endpoint c interrupt status. the bits in this register directly indicate the cause of the interrupt. when a bit in this register is set to 1, writing a 1 to the bit can clear the cause of the interrupt. bit 7 pingtranack this bit is set to 1 when an ack is returned to the host in a ping transaction. bit 6 outshortack this bit is set to 1 together with the outtranack bit when a short packet is received and an ack is returned in an out transaction. bit 5 intranack this bit is set to 1 when an ack is received from the host in an in transaction. bit 4 outtranack this bit is set to 1 when an ack is returned to the host in an out transaction. bit 3 intrannak this bit is set to 1 when an nak is returned to the host in an in transaction. bit 2 outtrannak this bit is set to 1 when an nak is returned to the host for an out or ping transaction. bit 1 intranerr this bit is set to 1 when either a stall is returned to the host, a packet error occurs or a handshake times out in an in transaction. bit 0 outtranerr this bit is set to 1 when a stall is returned to the host or a packet error is found in an out transaction. 7.2.13 0ch to 0fh reserved address register name r/w bit symbol description reset 0ch (reserved) 7: 0: 1: to 6: 0: 1: 0fh 5: 0: 1: 4: 0: 1: 3: 0: 1: 2: 0: 1: 1: 0: 1: 0: 0: 1: 00h 7.2.14 10h main interrupt enable (mainintenb) address register name r/w bit symbol d escription reset 10h mainintenb r/w 7: ensieintstat 0: disable 1: enable r/w 6: enbulkintstat 0: disable 1: enable r/w 5: eneprintstat 0: disable 1: enable r/w 4: enideintstat 0: disable 1: enable 3: 0: 1: r/w 2: enportintstat 0: disable 1: enable 1: 0: 1: r/w 0: enrcvep0setup 0: disable 1: enable 00h this register enables or disables the assertion of interrupt signals to the cpu in the mainintstat register. setting any bit in this register to 1 enables the corresponding interrupt to the cpu. the ensieintstat and enportintstat bits are effective even during snooze.
S1R72003 technical manual rev.1.0 epson 25 7.2.15 11h sie interrupt enable (sieintenb) address register name r/w bit symbol d escription reset 11h sieintenb r/w 7: envbuschanged 0: disable 1: enable r/w 6: ennon_j 0: disable 1: enable r/w 5: endetectreset 0: disable 1: enable r/w 4: endetectsuspend 0: disable 1: enable r/w 3: enrcvsof 0: disable 1: enable r/w 2: enchirpcmp 0: disable 1: enable r/w 1: enrestorecmp 0: disable 1: enable 0: 0: 1: 00h this register enables or disables the causes of the interrupts in the sieintstat register. when a bit is set to 1, the mainint stat register sieintstat bit will be set to 1 when the corresponding cause of the interrupt occurs. the envbuschanged and ennon_j bits are effective even during snooze. 7.2.16 12h bulk interrupt enable (bulkintenb) address register name r/w bit symbol description reset 12h bulkintenb r/w 7: encbwcmp 0: disable 1: enable r/w 6: encbwshort 0: disable 1: enable r/w 5: encbwlong 0: disable 1: enable r/w 4: encbwerr 0: disable 1: enable r/w 3: encswcmp 0: disable 1: enable r/w 2: encswerr 0: disable 1: enable r/w 1: enbulkincmp 0: disable 1: enable r/w 0: enbulkoutcmp 0: disable 1: enable 00h this register enables or disables the causes of the interrupts in the bulkintstat register. when a bit is set to 1, the mainin tstat register bulkintstat bit will be set to 1 when the corresponding cause of the interrupt occurs. 7.2.17 13h epr interrupt enable (eprintenb) address register name r/w bit symbol d escription reset 13h eprintenb 7: 0: 1: 6: 0: 1: 5: 0: 1: 4: 0: 1: r/w 3: enep0intstat 0: disable 1: enable r/w 2: enepaintstat 0: disable 1: enable r/w 1: enepbintstat 0: disable 1: enable r/w 0: enepcintstat 0: disable 1: enable 00h this register enables or disables the causes of the interrupts in the eprintstat register. when a bit is set to 1, the mainint stat register eprintstat bit will be set to 1 when the corresponding cause of the interrupt occurs. 7.2.18 14h ide interrupt enable (ideintenb) address register name r/w bit symbol description reset 14h ideintenb 7: 0: 1: 6: 0: 1: 5: 0: 1: 4: 0: 1: 3: 0: 1: r/w 2: endtcmp 0: disable 1: enable r/w 1: endetectintrq 0: disable 1: enable r/w 0: endetectterm 0: disable 1: enable 00h this register enables or disables the causes of the interrupts in the ideintstat register. when a bit is set to 1, the mainint stat register ideintstat bit will be set to 1 when the corresponding cause of the interrupt occurs.
S1R72003 technical manual 26 epson rev.1.0 7.2.19 15h reserved address register name r/w bit symbol description reset 15h (reserved) 7: 0: 1: 6: 0: 1: 5: 0: 1: 4: 0: 1: 3: 0: 1: 2: 0: 1: 1: 0: 1: 0: 0: 1: 00h 7.2.20 16h port interrupt enable (portintenb) address register name r/w bit symbol description reset 16h portintenb 7: 0: 1: 6: 0: 1: 5: 0: 1: 4: 0: 1: 3: 0: 1: 2: 0: 1: r/w 1: enportint1 0: disable 1: enable r/w 0: enportint0 0: disable 1: enable 00h this register enables or disables the causes of the interrupts in the portintstat register. when a bit is set to 1, the mainin tstat register portintstat bit will be set to 1 when the corresponding cause of the interrupt occurs. this register is effective even during snooze. 7.2.21 17h reserved address register name r/w bit symbol description reset 17h (reserved) 7: 0: 1: 6: 0: 1: 5: 0: 1: 4: 0: 1: 3: 0: 1: 2: 0: 1: 1: 0: 1: 0: 0: 1: 00h 7.2.22 18h ep0 interrupt enable (ep0intenb) address register name r/w bit symbol description reset 18h ep0intenb r/w 7: enpingtranack 0: disable 1: enable 6: 0: 1: r/w 5: enintranack 0: disable 1: enable r/w 4: enouttranack 0: disable 1: enable r/w 3: enintrannak 0: disable 1: enable r/w 2: enouttrannak 0: disable 1: enable r/w 1: enintranerr 0: disable 1: enable r/w 0: enouttranerr 0: disable 1: enable 00h this register enables or disables the causes of the interrupts in the ep0intstat register. when a bit is set to 1, the eprints tat register ep0intstat bit will be set to 1 when the corresponding cause of the interrupt occurs.
S1R72003 technical manual rev.1.0 epson 27 7.2.23 19h epa interrupt enable (epaintenb) address register name r/w bit symbol d escription reset 19h epaintenb r/w 7: enpingtranack 0: disable 1: enable r/w 6: enoutshortack 0: disable 1: enable r/w 5: enintranack 0: disable 1: enable r/w 4: enouttranack 0: disable 1: enable r/w 3: enintrannak 0: disable 1: enable r/w 2: enouttrannak 0: disable 1: enable r/w 1: enintranerr 0: disable 1: enable r/w 0: enouttranerr 0: disable 1: enable 00h this register enables or disables the causes of the interrupts in the epaintstat register. when a bit is set to 1, the eprints tat register epaintstat bit will be set to 1 when the corresponding cause of the interrupt occurs. 7.2.24 1ah epb interrupt enable (epbintenb) address register name r/w bit symbol description reset 1ah epbintenb r/w 7: enpingtranack 0: disable 1: enable r/w 6: enoutshortack 0: disable 1: enable r/w 5: enintranack 0: disable 1: enable r/w 4: enouttranack 0: disable 1: enable r/w 3: enintrannak 0: disable 1: enable r/w 2: enouttrannak 0: disable 1: enable r/w 1: enintranerr 0: disable 1: enable r/w 0: enouttranerr 0: disable 1: enable 00h this register enables or disables the causes of the interrupts in the epbintstat register. when a bit is set to 1, the eprints tat register epbintstat bit will be set to 1 when the corresponding cause of the interrupt occurs. 7.2.25 1bh epc interrupt enable (epcintenb) address register name r/w bit symbol d escription reset 1bh epcintenb r/w 7: enpingtranack 0: disable 1: enable r/w 6: enoutshortack 0: disable 1: enable r/w 5: enintranack 0: disable 1: enable r/w 4: enouttranack 0: disable 1: enable r/w 3: enintrannak 0: disable 1: enable r/w 2: enouttrannak 0: disable 1: enable r/w 1: enintranerr 0: disable 1: enable r/w 0: enouttranerr 0: disable 1: enable 00h this register enables or disables the causes of the interrupts in the epcintstat register. when a bit is set to 1, the eprints tat register epcintstat bit will be set to 1 when the corresponding cause of the interrupt occurs. 7.2.26 1ch to 1fh reserved address register name r/w bit symbol description reset 1ch (reserved) 7: 0: 1: to 6: 0: 1: 1fh 5: 0: 1: 4: 0: 1: 3: 0: 1: 2: 0: 1: 1: 0: 1: 0: 0: 1: 00h
S1R72003 technical manual 28 epson rev.1.0 7.2.27 20h chip reset (chipreset) address register name r/w bit symbol description reset 20h chipreset 7: 0: 1: 6: 0: 1: 5: 0: 1: 4: 0: 1: 3: 0: 1: 2: 0: 1: w 1: resetsie 0: normal 1: sie reset w 0: resetall 0: normal 1: all reset 00h this register resets the S1R72003f00b100. bit 7 reserved bit 6 reserved bit 5 reserved bit 4 reserved bit 3 reserved bit 2 reserved bit 1 resetsie resets the sie block of the S1R72003f00b100. setting this bit to 1 resets the usbaddress register, ep0setup_0 through 7 registers, and the framenumber_h and l registers to their initial values. this bit is automatically cleared to 0 upon completion of initialization. bit 0 resetall resets the sequencer of the S1R72003f00b100. setting this bit to 1 resets all but a few registers to their initial values. this bit is automatically cleared to 0 upon completion of initialization. the register bits that can be accessed during snooze and the mainintenb register are not reset. 7.2.28 21h revision number (revisionnum) address register name r/w bit symbol d escription reset 21h revisionnum 7: revisionnum[7] 6: revisionnum[6] 5: revisionnum[5] 4: revisionnum[4] 3: revisionnum[3] 2: revisionnum[2] 1: revisionnum[1] r 0: revisionnum[0] revision number 31h this register shows the revision number of the S1R72003f00b100. this register is effective even during snooze.
S1R72003 technical manual rev.1.0 epson 29 7.2.29 22h power management control (pmcontrol) address register name r/w bit symbol description reset 22h pmcontrol r 7: insnooze 0: normal 1: in snooze 6: 0: 1: 5: 0: 1: r/w 4: resetutm 0: normal 1: utmi reset r/w 3: pllsel 0: select pll480mhz 1: select pll60mhz r/w 2: sleepenb 0: disable osc stop at sleep 1:enable osc stop at sleep r/w 1: analogpwdown 0: disable analog power down 1:enable analog power down r/w 0: snooze 0: normal 1: snooze 00h this register sets the power management-related operations of the S1R72003f00b100. this register is effective even during snooze. bit 7 insnooze this bit is set to 1 when the S1R72003f00b100 is pl aced in the s nooze state by the pmcontrol register snooze bit. this bit is reset to 0 when clk output stabilizes after the S1R72003f00b100 is freed from the snooze state by clearing the snooze bit to 0. bit 6 reserved bit 5 reserved bit 4 resetutm the utm block of the S1R72003f00b100 can be reset by setting this bit to 1. to d eactivate the reset state, clear this bit to 0. bit 3 pllsel sets one of two pll types in the S1R72003f00b100. 0: select pll 480 mhz. 1: select pll 60 mhz. pll480 is available in any mode. pll60 is available in the fs mode only. before starting chirp after detecting the usb reset state, select pll 480 mhz by setting this bit to 0. bit 2 sleepenb sets whether or not to halt the oscillation circuit when the xsleep pin is activated during snooze. 0: do not halt the oscillation circuit when the xsleep pin is activated during snooze. 1: halt the oscillation circuit when the xsleep pin is activated during snooze. the device is restored from the sleep state when an interrupt cause that is effective even during sleep arises. in this case, the S1R72003f00b100 operates in the manner described below. 1) an interrupt cause arises (interrupt cause effective even during sleep: vbuschanged, non_j, port1, and port0). 2) restore the oscillation circuit. 3) wait until the oscillation circuit stabilizes. (the wait time depends on the crystal oscillation circuit and should be evaluated on the board.) 4) assert the xint signal. 5) the cpu negates the xsleep pin. the current consumption in the S1R72003f00b100 can be reduced to several ma by turning the oscillation circuit off during sleep. bit 1 analogpwdown controls whether or not to enable the analogfrontend unit of the internal transceiver macro. 0: disable the analogfrontend unit of the internal transceiver macro. 1: enable the analogfrontend unit of the internal transceiver macro. if no cables are connected (i.e., usbstatus register vbus bit is 0) and the S1R72003f00b100 is pl aced in the s nooze state by setting the pmcontrol register snooze bit, the device power consumption can be further reduced by setting this bit to 1. in this case, the current consumption in the S1R72003f00b100 is reduced to several ma. bit 0 snooze setting this bit to 1 halts the pll oscillation in the S1R72003f00b100 (snooze mode). the snooze mode is used to reduce the current consumption when the suspend state is detected on the usb. to enter the snooze mode, set the usbcontrol register disbusdetect bit to 1. set the disbusdetect bit to 1 before setting the snooze bit to 1. only specific registers can be accessed during s nooze. for information on which registers are effective even during snooze, refer to the description of the registers. because the usb reset state detection by the sieintstat register detectreset bit does not work during snooze, check the usbstatus register linestate bit to determine whether the detection of a request for usb reset or suspend state deactivation (resume) is possible. set this bit to 0 to deactivate the suspend state. after confirming that the insnooze bit is cleared to 0, perform the necessary processing using the usbcontrol register gochirp bit for reset or the restoreusb bit for resume. then set the disbusdetect bit to 0 to allow detection of the usb reset or suspend state. 0: deactivate the snooze state. 1: activate the snooze state.
S1R72003 technical manual 30 epson rev.1.0 7.2.30 23h usb control (usbcontrol) address register name r/w bit symbol description reset 23h usbcontrol r/w 7: disbusdetect 0: enable busdetect 1: disable busdetect 6: 0: 1: 5: 0: 1: 4: 0: 1: r/w 3: sendwakeup 0: normal 1:send remotewakeup signal r/w 2: restoreusb 0: normal 1: restore usb r/w 1: gochirp 0: normal 1: go chirp r/w 0: activeusb 0: in active usb 1: active usb 00h this register sets the usb-related operations of the S1R72003f00b100. bit 7 disbusdetect setting this bit to 1 nullifies usb reset/suspend detection. 0: automatically detect the usb reset/suspend state. 1: do not automatically detect the usb reset/suspend state. when this bit is cleared to 0, the device monitors activity on the usb bus. if no bus activity is detected for 3 ms or longer in the hs mode, the device automatically switches mode to fs, identifies the state as a reset or suspend state, and sets the relevant interrupt cause (detectreset or detectsuspend). if no bus activity is detected for 3 ms or longer in the fs mode, the state is identified as a suspend state. if se0 lasting 2.5 s or longer is detected, the state is identified as a reset state. once a reset or suspend state is detected (immediately after the detectreset or detectsuspend interrupt cause bit is set to 1), set the disbusdetect to 1 to disable the usb reset/suspend state detection. bit 6 reserved bit 5 reserved bit 4 reserved bit 3 sendwakeup setting this bit to 1 causes the remotewakeup signal (fs-k/hs-k) to be output to the usb port. 0: perform no operation. 1: send the remotewakeup signal. when 1 ms or longer (max. 15 ms) has elapsed after sending the remotewakeup signal, clear this bit to 0 to stop sending the signal. note that the device must be restored from the snooze state before this bit can be set to 1. (this operation can only be performed when the pmcontrol register insnooze bit is 0.) bit 2 restoreusb if this bit is set to 1 when the usb is resumed from the suspend state, it returns to the previous operation mode (fs or hs) saved before it was suspended, and the relevant interrupt cause (restorecmp) is set. this bit is automatically cleared to 0 when the operation is finished. note that the device must be restored from the snooze state before this bit can be set to 1. (this operation can only be performed when the pmcontrol register insnooze bit is 0.) 0: perform no operation. 1: restore the usb operation mode where it was placed before the suspend state. bit 1 gochirp if this bit is set to 1 while the usb bus is in the reset state, hs detection handshake between the host and hub is performed, setting the xcvrcontrol register termselect and xcvrselect bits, and the usbstatus register fsxhs bit automatically. the interrupt cause (chirpcmp) is set upon completion of the above operation. this bit is automatically cleared to 0 after the operation is finished. the result of negotiation can be confirmed by inspecting the usbstatus register fsxhs bit after the end of operation. 0: perform no operation. 1: start hs detection handshake operation. bit 0 activeusb when the S1R72003f00b100 is reset in hardware, this bit is cleared to 0, with all usb functions turned off. the usb can be enabled by setting this bit to 1 after setting up the S1R72003f00b100. 0: do not enable usb functions/operation. 1: enable usb functions/operation.
S1R72003 technical manual rev.1.0 epson 31 7.2.31 24h usb status (usbstatus) address register name r/w bit symbol description reset 24h usbstatus r 7: vbus 0: vbus = l 1: vbus = h r/(w) 6: fsxhs 0: hs 1: fs 5: 0: 1: 4: 0: 1: 3: 0: 1: 2: 0: 1: 1: linestate[1] r 0: linestate[0] line state xxh this register shows the usb related status. this register is effective even during snooze. bit 7 vbus reflects the vbus pin status directly as is. 0: not connected. 1: connected. bit 6 fsxhs indicates the current usb operation mode. by setting this bit, the operation mode can be changed forcibly. usually, the user do not have to set this bit since it is automatically set after hs detection handshake (see appendix a.3.). 0: hs mode 1: fs mode bit 5 reserved bit 4 reserved bit 3 reserved bit 2 reserved bits 1-0 linestate [1:0] indicates the usb cable signal status. when the xcvrcontrol register termselect bit = 1 (fs termination selected), if the xcvrselect bit is 1 (fs transceiver selected), linestate indicates the received value of the dp/dm fs single-end receiver; if xcvrselect is 0 (hs transceiver selected), it indicates the received value of the hs differential receiver. when termselect = 0, linestate indicates 0b11. linestate termselect dp / dm linestate[1:0] 0 don?t care 0b11 1 se0 0b00 1 j 0b01 1 k 0b10 1 se1 0b11
S1R72003 technical manual 32 epson rev.1.0 7.2.32 25h xcvr control (xcvrcontrol) address register name r/w bit symbol description reset 25h xcvrcontrol r/w 7: termselect 0: hs 1: fs r/w 6: xcvrselect 0: hs 1: fs 5: 0: 1: 4: 0: 1: 3: 0: 1: 2: 0: 1: 1: opmode[1] r/w 0: opmode[0] opmode 41h this register sets the parameters associated with the transceiver macro. bit 7 termselect sets either fs or hs termination as the valid termination. this bit is automatically set when hs detection handshake is performed by the usbcontrol register gochirp bit. 0: hs 1: fs bit 6 xcvrselect sets either fs or hs transceiver as the valid transceiver. this bit is automatically set when hs detection handshake is performed by the usbcontrol register gochirp bit. 0: hs 1: fs bit 5 reserved bit 4 reserved bit 3 reserved bit 2 reserved bits 1-0 opmode sets the operation mode of the transceiver macro. opmode 00 ?normal operation? 01 ?non-driving? 10 ?disable bitstuffing and nrzi encoding? 11 ?reserved?
S1R72003 technical manual rev.1.0 epson 33 7.2.33 26h usb test (usbtest) address register name r/w bit symbol description reset 26h usbtest r/w 7: enhstest 0: normal 1: enable hs test mode 6: 0: 1: 5: 0: 1: 4: 0: 1: r/w 3: se0_nak 0: normal 1: se0 nak r/w 2: test_j 0: normal 1: test j r/w 1: test_k 0: normal 1: test k r/w 0: testpacket 0: normal 1: test packet 00h this register sets the parameters associated with usb 2.0 test mode. when the operation mode is ?hs,? set the bit correspondin g to the test mode specified by a setfeature request, and then set the enhstest bit to 1 after the status stage is finished. the de vice can be operated in the test mode defined under the usb 2.0 specification. bit 7 enhstest setting this bit to 1 while one of the 4 low-order bits of the usbtest register is set to 1 places the device in the test mode corresponding to that bit. to run a device in the test mode, set the usbcontrol register disbusdetect bit to 1 to disable usb reset/suspend state detection. bit 6 reserved bit 5 reserved bit 4 reserved bit 3 se0_nak setting this bit to 1, then setting the enhstest bit to 1 places the device in se0_nak test mode. bit 2 test_j setting this bit to 1, and then setting the enhstest bit to 1 places the device in hs j test mode. note that opmode must be set to 10 (disable bitstuffing and nrzi encoding) before the enhstest bit is set to 1. bit 1 test_k setting this bit to 1, and then setting the enhstest bit to 1 places the device in hs k test mode. note that opmode must be set to 10 (disable bitstuffing and nrzi encoding) before the enhstest bit is set to 1. bit 0 testpacket setting this bit to 1, and then setting the enhstest bit to 1 places the device in packet transmit test mode. because epc is used when operating in this test mode, several settings are required. the procedure is described below. 1) to enable epc, set maxpacketsize of epc to 64 or more, the transfer direction to in, and endpointnumber of epc to 15. 2) clear the epaconfig_1 and epbconfig_1 register enendpoint bits to 0. then set the epcconfig_1 register enendpoint bit to 1. 3) clear the fifo of epc and write the test packet data in this fifo. 4) clear the epcintenb register enintranerr bit to 0. shown below are the data to be written to the fifo during packet transmit test mode: 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, aah, aah, aah, aah, aah, aah, aah, aah, eeh, eeh, eeh, eeh, eeh, eeh, eeh, eeh, feh, ffh, ffh, ffh, ffh, ffh, ffh, ffh, ffh, ffh, ffh, ffh, 7fh, bfh, dfh, efh, f7h, fbh, fdh, fch, 7eh, bfh, dfh, efh, f7h, fbh, fdh, 7eh when sending a test packet, the sie adds pid and crc to the transmit data. a range of test packet data specified in the usb specification must be written to the fifo, from the data immediately following data0 pid to the data preceding crc16.
S1R72003 technical manual 34 epson rev.1.0 7.2.34 27h reserved address register name r/w bit symbol description reset 27h (reserved) 7: 0: 1: 6: 0: 1: 5: 0: 1: 4: 0: 1: 3: 0: 1: 2: 0: 1: 1: 0: 1: 0: 0: 1: 00h 7.2.35 28h usb address (usbaddress) address register name r/w bit symbol description reset 28h usbaddress 7: 0: 1: 6: usbaddress[6] 5: usbaddress[5] 4: usbaddress[4] 3: usbaddress[3] 2: usbaddress[2] 1: usbaddress[1] r/w 0: usbaddress[0] usb address 00h this register sets the usb address. bit 7 reserved bits 6-0 usbaddress sets the usb address. the address to be set in these bits is specified by the host after the status stage of a setaddress request is finished.
S1R72003 technical manual rev.1.0 epson 35 7.2.36 29h epr control (eprcontrol) address register name r/w bit symbol description reset 29h eprcontrol r 7: dmarunning 0: dma not running 1: dma running 6: 0: 1: 5: 0: 1: w 4: allfifoclr 0: normal 1: fifo clear 3: 0: 1: r/w 2: autoenshort 0: disable autoenshort 1: enable autoenshort r/w 1: allforcenak 0: normal 1: allforcenak r/w 0: eprforcestall 0: normal 1: eprforcestall 00h this register sets and indicates the general endpoint operation. bit 7 dmarunning this bit is set to 1 while dma transfer is underway. for in transactions, this bit is cleared to 0 when the dma transfer is finished, with all packets remaining in the fifo thereby transmitted. for out transactions, this bit is cleared to 0 when the dma transfer is finished after all packets are received and the dtgo bit is set to 0. 0: dma not operating 1: dma operating bit 6 reserved bit 5 reserved bit 4 allfifoclr setting this bit to 1 clears the fifos for all endpoints. when the maxpacketsize or doublebuf bits have been set for each e ndpoint, always confirm that this bit is set to 1 to clear the fifos for all endpoints after this setting is made. this bit is automatically cleared to 0 after the fifo is cleared. bit 3 reserved bit 2 autoenshort sets the operation mode of short packet transfer during in transactions at the endpoint for which the ep[a,b,c]config_1 register joinide bit = 1. 0: when the data remaining in the fifo after the end of dma is smaller than maxpacketsize, the data in the fifo is not transferred until the enshortpkt bit of the relevant endpoint is set to 1. setting the enshortpkt bit to 1 using firmware causes data transfer in response to an in token from the host. upon su ccessful completion of the in transaction, the bulkintstat register bulkincmp bit is set to 1. 1: when the data remaining in the fifo after the end of dma is smaller than maxpacketsize, the enshortpkt bit of the relevant endpoint is automatically set to 1. the data in the fifo is transferred in response to an in token from the host. upon completion of the in transaction, the bulkintstat register bulkincmp bit is set to 1. check the transfer data size before starting dma transfer. set this bit when a short packet occurs. bit 1 allforcenak setting this bit to 1 allows the ep0control_0 register inforcenak and outforcenak bits, as well as the forcenak bits in all ep[a,b,c]_control1_0 registers, to be set to 1. bit 0 eprforcestall setting this bit to 1 allows the forcestall bits in all ep[a,b,c]_control1_0 registers to be set to 1.
S1R72003 technical manual 36 epson rev.1.0 7.2.37 2ah bulkonly control (bulkonlycontrol) address register name r/w bit symbol description reset 2ah bulkonlycontrol 7: 0: 1: 6: 0: 1: 5: 0: 1: 4: 0: 1: 3: 0: 1: r/w 2: gocbwmode 0: normal mode 1: cbw receive mode r/w 1: gocswmode 0: normal mode 1: csw transfer mode r/w 0: cswsel 0: select csw0_00 to csw0_12 1: select csw1_00 to csw1_12 00h this register sets the operations of the usb storage-class bulkonly transport protocol. bit 7 reserved bit 6 reserved bit 5 reserved bit 4 reserved bit 3 reserved bit 2 gocbwmode setting this bit to 1 places the device in the bulkonly transport protocol?s cbw receive mode. when 31 bytes of cbw are received normally from the host, the bulkintstat register?s cbwcmp interrupt is generated. the received data is stored in registers cbw_00 through cbw_30. if the r eceived data consists of less than 31 bytes, a cbwshort interrupt is generated. conversely, if the received data is larger than 31 bytes, a cbwlong interrupt is generated. if a stall is returned at the corresponding end point when cbw is r eceived, a cbwerr interrupt is generated. when a cbwcmp, cbwshort, or cbwlong interrupt is generated, the gocbwmode bit is automatically cleared. however, when a cbwerr interrupt is generated, the gocbwmode bit is not cleared. if data is received during cbw receive mode, the pingtranack, outshortack, intranack, outtranack, intrannak, outtrannak, intranerr, and outtranerr bits in the ep[a,b,c]intstat register that corresponds to the cbw endpoint remain unchanged (not set to 1) when cbw is received; only the cbwcmp, cbwshort, cbwlong, and cbwerr bits change state. maxpacketsize that specifies the endpoint required for r eceiving cbw must be set to 32, 64 or 512. the cbw r eceive function can be used for another purpose if the bulk out data size is 31 bytes. bit 1 gocswmode setting this bit to 1 places the device in the bulkonly transport protocol?s csw transmit mode. either registers csw0_00 through csw0_12 or registers csw1_00 through csw1_12 can be selected for transmit data using the cswsel bit. when an ack from the host is received after csw is transmitted, a cswcmp interrupt configured in the bulkintstat register is generated. when ack is not received, a cswerr interrupt is generated. after a cswcmp or cswerr interrupt is generated, the gocswmode bit is cleared to 0 and the gocbwmode bit is set to 1 and the device is automatically placed in cbw receive mode. during csw transmit mode, the pingtranack, outshortack, intranack, outtranack, intrannak, outtrannak, intranerr, and outtranerr bits in the ep[a,b,c]intstat register that corresponds to the csw endpoint remain unchanged (not set to 1); only the cswcmp and cswerr bits change state. maxpacketsize that specifies the endpoint required for transmitting csw must be set to 16, 32, 64 or 512. the csw transmit function can be used for another purpose if the bulk in data size is 13 bytes. bit 0 cswsel in the bulkonly transport protocol?s csw transmit mode, this bit sets the contents of the csw0_00 to csw0_12 registers or the contents of the csw1_00 to csw1_12 registers to be transmitted. 0: transmit the contents of the csw0_00 to csw0_12 registers. 1: transmit the contents of the csw1_00 to csw1_12 registers.
S1R72003 technical manual rev.1.0 epson 37 7.2.38 2bh bulkonly config (bulkonlyconfig) address register name r/w bit symbol description reset 2bh bulkonlyconfig 7: cbwepnumber[3] 6: cbwepnumber[2] 5: cbwepnumber[1] r/w 4: cbwepnumber[0] cbw endpoint number 3: cswepnumber[3] 2: cswepnumber[2] 1: cswepnumber[1] r/w 0: cswepnumber[0] csw endpoint number 00h this register sets the endpoint numbers used in the usb storage-class bulkonly transport protocol. bits 7-4 cbwepnumber these bits set the endpoint number of the bulk out endpoint n ecessary to receive the cbw used in the bulkonly transport protocol. any value in the range of 01 to 15 can be set in this register. bits 3-0 cswepnumber these bits set the endpoint number of the bulk in endpoint n ecessary to transmit the csw used in the bulkonly transport protocol. any value in the range of 01 to 15 can be set in this register. 7.2.39 2ch to 2eh reserved address register name r/w bit symbol description reset 2ch (reserved) 7: 0: 1: to 6: 0: 1: 2eh 5: 0: 1: 4: 0: 1: 3: 0: 1: 2: 0: 1: 1: 0: 1: 0: 0: 1: 00h
S1R72003 technical manual 38 epson rev.1.0 7.2.40 2fh chip config (chipconfig) address register name r/w bit symbol description reset 2fh chipconfig r/w 7: rdyxwait 0: xwait mode 1: ready mode r/w 6: waitmode 0: hiz ? 0 mode 1: 1-0 mode r/w 5: intmode 0: hiz ? 0 mode 1: 1-0 mode 4: 0: 1: 3: 0: 1: 2: 0: 1: 1: 0: 1: 0: 0: 1: 00h this register sets the operation mode of the xwait pin and the output of the xwait and xint pins. this register is effective even during snooze. bit 7 rdyxwait 0: serve as a wait signal for the cpu. this signal is asserted (low) when requesting the cpu to wait. in the circuitry, xwait is the logical or of the internal ready and xcs signals. 1: serve as a ready signal for the cpu. when the S1R72003f00b100 is ready for read or write, this signal is asserted (high). in the circuitry, this is the internal ready signal output directly from the xwait pin. bit 6 waitmode 0: xwait output is 0 or hi-z. 1: xwait output is 0 or 1. bit 5 intmode 0: xint output is 0 or hi-z. 1: xint output is 0 or 1. bit 4 reserved bit 3 reserved bit 2 reserved bit 1 reserved bit 0 reserved
S1R72003 technical manual rev.1.0 epson 39 7.2.41 30h to 37h ep0 setup0 to ep0 setup7 (ep0setup_0 to ep0setup_7) address register name r/w bit symbol description reset 30h ep0setup_0 7: ep0setup_n[7] to to 6: ep0setup_n[6] 37h ep0setup_7 5: ep0setup_n[5] 4: ep0setup_n[4] 3: ep0setup_n[3] 2: ep0setup_n[2] 1: ep0setup_n[1] r 0: ep0setup_n[0] endpoint 0 setup data 0 to endpoint 0 setup data 7 00h these registers are used to store data received in the e ndpoint 0 setup stage. ep0setup_0 bmrequesttype is set in this register. ep0setup_1 brequest is set in this register. ep0setup_2 the 8 low-order bits of wvalue are set in this register. ep0setup_3 the 8 high-order bits of wvalue are set in this register. ep0setup_4 the 8 low-order bits of windex are set in this register. ep0setup_5 the 8 high-order bits of windex are set in this register. ep0setup_6 the 8 low-order bits of wlength are set in this register. ep0setup_7 the 8 high-order bits of wlength are set in this register. 7.2.42 38h framenumber high (framenumber_h) address register name r/w bit symbol description reset 38h framenumber_h r 7: fninvalid 0: frame number valid 1: frame number invalid 6: 0: 1: 5: 0: 1: 4: 0: 1: 3: 0: 1: 2: framenumber[10] 1: framenumber[9] r 0: framenumber[8] frame number high 80h this register shows usb frame numbers. to acquire a frame number, access the framenumber_h and framenumber_l registers in pairs. be sure to access the framenumber_h register first. bit 7 fninvalid this bit is set to 1 when an error occurs in the sof packet received. 0: sof packet received normally. 1: error occurred when receiving a sof packet. bit 6 reserved bit 5 reserved bit 4 reserved bit 3 reserved bits 2-0 framenumber these bits store the 3 high-order bits of data that represent the framenumber field of the received sof packet.
S1R72003 technical manual 40 epson rev.1.0 7.2.43 39h framenumber low (framenumber_l) address register name r/w bit symbol description reset 39h framenumber_l 7: framenumber[7] 6: framenumber[6] 5: framenumber[5] 4: framenumber[4] 3: framenumber[3] 2: framenumber[2] 1: framenumber[1] r 0: framenumber[0] frame number low 00h this register acquires usb frame numbers. to acquire a frame number, access the framenumber_h and framenumber_l registers in pairs. be sure to access the framenumber_h register first. bits 7-0 framenumber these bits store the 8 low-order bits of data that represent the framenumber field of the received sof packet. 7.2.44 3ah to 3fh reserved address register name r/w bit symbol description reset 3ah (reserved) 7: 0: 1: to 6: 0: 1: 3fh 5: 0: 1: 4: 0: 1: 3: 0: 1: 2: 0: 1: 1: 0: 1: 0: 0: 1: 00h
S1R72003 technical manual rev.1.0 epson 41 7.2.45 40h ep0 config_0 (ep0control_0) address register name r/w bit symbol description reset 40h ep0config_0 r/w 7: inxout 0: out 1: in 6: 0: 1: 5: 0: 1: 4: 0: 1: 3: 0: 1: 2: 0: 1: 1: 0: 1: 0: 0: 1: 00h this register sets endpoint 0. bit 7 inxout sets the transfer direction of endpoint 0. 0: out direction 1: in direction when setting a value in this bit, determine the direction from the request received in the setup stage. if there is a data stage, use this bit to set the transfer direction in the data stage. then clear the ep0control_0 register?s inforcenak or outforcenak bit to 0 (whichever corresponds to the data stage transfer direction) to execute the data stage. when the data stage transfer direction is in after the completion of the data stage, the direction of the status stage is out. then the status stage can be executed by setting this bit to 0 and clearing the ep0control_0 register outforcenak bit to 0. when the data stage transfer direction is out or no data stages exist, the direction of the status stage is in. then the status stage can be executed by clearing the fifo of endpoint 0 to set this bit to 1 and clearing the ep0control_0 register inforcenak bit to 0 to set the inenshortpkt bit to 1. for in or out transactions in a direction different from that set in this bit, if the ep0control_0 register corresponding to that transaction direction has its inforcestall or outforcestall bits set, the transaction is responded by stall. otherwise, the transaction is responded by nak. bit 6 reserved bit 5 reserved bit 4 reserved bit 3 reserved bit 2 reserved bit 1 reserved bit 0 reserved 7.2.46 41h reserved address register name r/w bit symbol description reset 41h (reserved) 7: 0: 1: 6: 0: 1: 5: 0: 1: 4: 0: 1: 3: 0: 1: 2: 0: 1: 1: 0: 1: 0: 0: 1: 00h
S1R72003 technical manual 42 epson rev.1.0 7.2.47 42h ep0 control_0 (ep0control_0) address register name r/w bit symbol description reset 42h ep0control_0 r/w 7: autoforcenak 0: normal 1: auto forcenak r/w 6: inenshortpkt 0: normal 1: send shot packet 5: 0: 1: 4: 0: 1: r/w 3: inforcenak 0: normal 1: in forcenak r/w 2: inforcestall 0: normal 1: in forcestall r/w 1: outforcenak 0: normal 1: out forcenak r/w 0: outforcestall 0: normal 1: out forcestall 00h this register sets the operations associated with endpoint 0 transfer. bit 7 autoforcenak this bit automatically sets the ep0control_0 register?s inforcenak or outforcenak bit to 1 when the transaction completes normally. bit 6 inenshortpkt setting this bit to 1 allows the data in the current fifo to be transmitted as a short packet for an in transaction. this bit is automatically cleared to 0 when the packet transfer is finished. if this bit is set to 1 when no data exists in the fifo, a packet of zero length is transmitted in response to an in token from the host. bit 5 reserved bit 4 reserved bit 3 inforcenak setting this bit to 1 causes in transaction to be responded by nak, regardless of the data count in the fifo. when the mainintstat register rcvep0setup bit is set to 1 upon completion of the setup stage, the inforcenak bit is automatically set to 1. this bit cannot be cleared to 0 while the mainintstat register rcvep0setup bit is 1. if the data stage transfer direction is in, the data stage can be executed by setting the ep0config_0 register inxout bit for in direction, and then clearing this bit to 0. if the data stage transfer direction is out, the status stage can be executed by clearing this bit to 0 after the status stage is ready to run. if any transaction is currently underway and this bit was set a certain time after the transaction started, the bit setting takes effect from the following transaction. bit 2 inforcestall setting this bit to 1 causes in transaction to be responded by stall. this bit is given priority over the inforcenak bit. when the mainintstat register rcvep0setup bit is set to 1 upon completion of the setup stage, the inforcestall bit is set to 0. this bit cannot be set to 1 while the mainintstat register rcvep0setup bit is 1. if any transaction is currently underway and this bit was set a certain time after the transaction started, the bit setting takes effect from the following transaction. bit 1 outforcenak setting this bit to 1 makes a nak response to the out transaction regardless of the free sp ace in the fifo. when the mainintstat register rcvep0setup bit is set to 1 upon completion of the setup stage, the outforcenak bit is automatically set to 1. this bit cannot be cleared to 0 while the mainintstat register rcvep0setup bit is 1. if the data stage transfer direction is out, the data stage can be executed by setting the ep0config_0 register inxout bit for out direction, and then clearing this bit to 0. if the data stage transfer direction is in, the status stage can be executed by clearing this bit to 0 after the status stage is ready to run. if any transaction is currently underway and this bit was set a certain time after the transaction started, the bit setting takes effect from the following transaction. bit 0 outforcestall setting this bit to 1 causes out transaction to be responded by stall. this bit is given priority over the outforcenak bit. when mainintstat register rcvep0setup bit is set to 1 upon completion of the setup stage, the outforcestall bit is set to 0. this bit cannot be set to 1 while the mainintstat register rcvep0setup bit is 1. if any transaction is currently underway and this bit was set a certain time after the transaction started, the bit setting takes effe ct from the following transaction.
S1R72003 technical manual rev.1.0 epson 43 7.2.48 43h ep0 control_1 (ep0control_1) address register name r/w bit symbol description reset 43h ep0control_1 r 7: intogglestat in toggle status 6: 0: 1: r/w 5: intoggleset 0: normal 1: in transaction toggle set r/w 4: intoggleclr 0: normal 1:intransaction toggle clear r 3: outtogglestat out toggle status 2: 0: 1: r/w 1: outtoggleset 0: normal 1:outtransaction toggle set r/w 0: outtoggleclr 0: normal 1:outtransactiontoggleclear 00h this register shows or sets the operations associated with endpoint 0 toggle bits. bit 7 intogglestat shows the status of the in transaction toggle sequence bit. bit 6 reserved bit 5 intoggleset sets the in transaction toggle sequence bit to 1. bit 4 intoggleclr clears the in transaction toggle sequence bit to 0. bit 3 outtogglestat shows the status of the out transaction toggle sequence bit. bit 2 reserved bit 1 outtoggleset sets the out transaction toggle sequence bit to 1. bit 0 outtoggleclr clears the out transaction toggle sequence bit to 0. 7.2.49 44h reserved address register name r/w bit symbol description reset 44h (reserved) 7: 0: 1: 6: 0: 1: 5: 0: 1: 4: 0: 1: 3: 0: 1: 2: 0: 1: 1: 0: 1: 0: 0: 1: 00h 7.2.50 45h ep0 fifo remain (ep0fiforemain) address register name r/w bit symbol description reset 45h ep0fiforemain 7: 0: 1: 6: ep0fiforemaincounter[6] 5: ep0fiforemaincounter[5] 4: ep0fiforemaincounter[4] 3: ep0fiforemaincounter[3] 2: ep0fiforemaincounter[2] 1: ep0fiforemaincounter[1] r 0: ep0fiforemaincounter[0] endpoint 0 fifo remain counter 00h this register shows the number of data bytes in the endpoint 0 fifo. bit 7 reserved bit 6-0 ep0fiforemaincounter these bits show the number of data bytes remaining in the endpoint 0 fifo. when accessing the fifo from the cpu, inspect this register to check the data counts.
S1R72003 technical manual 44 epson rev.1.0 7.2.51 46h ep0 fifoforcpu (ep0fifoforcpu) address register name r/w bit symbol description reset 46h ep0fifoforcpu 7: ep0fifodata[7] 6: ep0fifodata[6] 5: ep0fifodata[5] 4: ep0fifodata[4] 3: ep0fifodata[3] 2: ep0fifodata[2] 1: ep0fifodata[1] r/w 0: ep0fifodata[0] endpoint 0 fifo access from cpu xxh this register is used for fifo access from the cpu. when the ep0fifocontrol register enfifowr bit is set to 1, data can be written into the fifo by writing a value in this registe r. when the ep0fifocontrol register enfiford bit is set to 1, data can be read from the fifo by reading the value from this regist er. if a value is written in this register without setting the enfifowr bit, writing in the fifo is not executed. if a value is re ad from the register without setting the enfiford bit, dummy data is output. 7.2.52 47h ep0 fifo control (ep0fifocontrol) address register name r/w bit symbol description reset 47h ep0fifocontrol r 7: fifoempty 0: fifo not empty 1: fifo empty r 6: fifofull 0: fifo not full 1: fifo full 5: 0: 1: 4: 0: 1: 3: 0: 1: w 2: fifoclr 0: normal 1: fifo clear r/w 1: enfifowr 0: normal 1: enable fifo write r/w 0: enfiford 0: normal 1: enable fifo read 80h this register acquires or sets the endpoint 0 fifo status. bit 7 fifoempty when this bit = 1, the fifo is empty. before reading data from the fifo, check to see that this bit = 0. bit 6 fifofull when this bit = 1, the fifo is full. before writing data into the fifo, check to see that this bit = 0. bit 5 reserved bit 4 reserved bit 3 reserved bit 2 fifoclr setting this bit to 1 clears the fifo. this bit is automatically cleared to 0 after the fifo is cleared. bit 1 enfifowr setting this bit to 1 allows data to be written into the fifo by the cpu. this bit cannot be set to 1 when the enfiford bit is 1. bit 0 enfiford setting this bit to 1 allows data to be read from the fifo by the cpu. this bit cannot be set to 1 when the enfifowr bit is 1. 7.2.53 48h to 4fh reserved address register name r/w bit symbol description reset 48h (reserved) 7: 0: 1: to 6: 0: 1: 4fh 5: 0: 1: 4: 0: 1: 3: 0: 1: 2: 0: 1: 1: 0: 1: 0: 0: 1: 00h
S1R72003 technical manual rev.1.0 epson 45 7.2.54 50h epa config_0 (epaconfig_0) address register name r/w bit symbol description reset 50h epaconfig_0 r/w 7: inxout 0: out 1: in 6: 0: 1: 5: 0: 1: 4: 0: 1: 3: endpointnumber[3] 2: endpointnumber[2] 1: endpointnumber[1] r/w 0: endpointnumber[0] endpoint number 00h this register sets endpoint a. bit 7 inxout sets the transfer direction of the endpoint. 0: out direction 1: in direction bit 6 reserved bit 5 reserved bit 4 reserved bits 3-0 endpointnumber these bits set an endpoint number in the range from 01 to 15.
S1R72003 technical manual 46 epson rev.1.0 7.2.55 51h epa config_1 (epaconfig_1) address register name r/w bit symbol description reset 51h epaconfig_1 r/w 7: joinide 0: not join ide 1: join ide r/w 6: togglemode 0: 1: r/w 5: enendpoint 0: disable endpoint 1: enable endpoint r/w 4: doublebuf 0: single buffer 1: double buffer 3: 0: 1: 2: maxpacketsize[2] 1: maxpacketsize[1] r/w 0: maxpacketsize[0] max packet size 00h this register sets endpoint a. bit 7 joinide connects the endpoint to dma. dma connects to the last endpoint that has had this bit set to 1. immediately following the reset, the joinide bit is 0 for all endpoints. 0: do not connect this endpoint to dma. 1: connect this endpoint to dma. bit 6 togglemode sets the operation mode of the toggle bit (in transaction only). 0: toggle only when the transaction terminates normally. 1: always toggle for each transaction performed. bit 5 enendpoint setting this bit to 1 enables the endpoint. a ccesses to the endpoint are ignored when this bit = 0. set the appropriate value in this bit following the setconfiguration request from the host. 0: disables the endpoint. 1: enables the endpoint. bit 4 doublebuf setting this bit to 1 configures the fifo for the endpoint as double buffers. a memory space twice the size set by maxpacketsize is reserved in the fifo. 0: configure the fifo as a single buffer. 1: configure the fifo as double buffers. bit 3 reserved bits 2-0 maxpacketsize sets the maximum value of the packet size. the relationship between the set values and the packet sizes is shown below. (bit 2, 1, 0) maxpacketsize fs hs 000 reserved reserved 001 8 bytes 8 bytes 010 16 bytes 16 bytes 011 32 bytes 32 bytes 100 64 bytes 64 bytes 101 512 bytes 110 111 reserved 1024 bytes the settings other than 512 bytes in the hs mode are used in interrupt transfers. use epc when isochronous transfer is desired. after setting maxpacketsize and doublebuf for the endpoints, be sure to set the eprcontrol register allfifoclr bit to 1 to clear all fifos. in addition, ensure that the total fifo area reserved by endpoints a, b, c does not ex ceed 2432 bytes.
S1R72003 technical manual rev.1.0 epson 47 7.2.56 52h epa control_0 (epacontrol_0) address register name r/w bit symbol description reset 52h epacontrol_0 r/w 7: autoforcenak 0: normal 1: autoforcenak w 6: enshortpkt 0: normal 1: send short packet r/w 5: autoforcenakshort 0: normal 1: autoforcenakshort 4: 0: 1: 3: 0: 1: 2: 0: 1: r/w 1: forcenak 0: normal 1: forcenak r/w 0: forcestall 0: normal 1: forcestall 00h this register sets the operation of endpoint a. bit 7 autoforcenak this bit automatically sets the epacontrol_0 register?s forcenak bit to 1 when the transaction completes normally. 0: do not automatically set the forcenak bit. 1: automatically set the forcenak bit. bit 6 enshortpkt(in transaction only) setting this bit to 1 allows the data in the current fifo to be transmitted as a short packet for an in transaction. this bit is automatically cleared to 0 when the packet transfer is finished. if this bit is set to 1 when no data exists in the fifo, a packet of zero length is transmitted in response to an in token from the host. bit 5 autoforcenakshort when this bit = 1, if the packet received during an out transaction that completed normally is a short packet, the forcenak bit is automatically set to 1. if the autoforcenak bit = 1, autoforcenak has priority over this bit. 0: do not automatically set the forcenak bit to 1. 1: automatically set the forcenak bit to 1. bit 4 reserved bit 3 reserved bit 2 reserved bit 1 forcenak setting this bit to 1 makes a nak response to the transaction regardless of the data count and free sp ace in the fifo. if any transaction is currently underway and this bit was set a certain time after the transaction started, the bit setting takes effect in the subsequent transactions. bit 0 forcestall setting this bit to 1 causes the transaction to be responded by stall. this bit is given priority over the forcenak bit. if any transaction is currently underway and this bit was set a certain time after the transaction started, the bit setting takes effect from the following transaction.
S1R72003 technical manual 48 epson rev.1.0 7.2.57 53h epa control_1 (epacontrol_1) address register name r/w bit symbol description reset 53h epacontrol_1 7: 0: 1: 6: 0: 1: 5: 0: 1: 4: 0: 1: r 3: togglestat toggle status 2: 0: 1: w 1: toggleset 0: normal 1: toggle set w 0: toggleclr 0: normal 1: toggle clear 00h this register indicates and controls the status of the endpoint a toggle bit. bit 7 reserved bit 6 reserved bit 5 reserved bit 4 reserved bit 3 togglestat shows the status of the toggle sequence bit. bit 2 reserved bit 1 toggleset setting this bit to 1 sets the toggle sequence bit to 1. bit 0 toggleclr setting this bit to 1 clears the toggle sequence bit to 0. 7.2.58 54h epa fifo remain high (epafiforemain_h) address register name r/w bit symbol description reset 54h epafiforemain_h 7: epafiforemaincounter[15] 6: epafiforemaincounter[14] 5: epafiforemaincounter[13] 4: epafiforemaincounter[12] 3: epafiforemaincounter[11] 2: epafiforemaincounter[10] 1: epafiforemaincounter[9] r 0: epafiforemaincounter[8] endpoint a fifo remain counter high 00h this register shows the eight high-order bits that represent the remaining data counts in the endpoint a fifo. to acquire the fifo?s remaining data counts, access the epafiforemain_h and epafiforemain_l registers in pairs. be sure to access the epafiforemain_h register first. 7.2.59 55h epa fifo remain low (epafiforemain_l) address register name r/w bit symbol description reset 55h epafiforemain_l 7: epafiforemaincounter[7] 6: epafiforemaincounter[6] 5: epafiforemaincounter[5] 4: epafiforemaincounter[4] 3: epafiforemaincounter[3] 2: epafiforemaincounter[2] 1: epafiforemaincounter[1] r 0: epafiforemaincounter[0] endpoint a fifo remain counter low 00h this register shows the eight low-order bits that represent the remaining data counts in the endpoint a fifo. to acquire the f ifo?s remaining data counts, access the epafiforemain_h and epafiforemain_l registers in pairs. be sure to access the epafiforemain_h register first.
S1R72003 technical manual rev.1.0 epson 49 7.2.60 56h epa fifo for cpu (epafifoforcpu) address register name r/w bit symbol description reset 56h epafifoforcpu 7: epafifodata[7] 6: epafifodata[6] 5: epafifodata[5] 4: epafifodata[4] 3: epafifodata[3] 2: epafifodata[2] 1: epafifodata[1] r/w 0: epafifodata[0] endpoint a fifo access from cpu xxh this register is used for fifo access from the cpu. when the epafifocontrol register enfifowr bit is set to 1, data can be written into the fifo by writing a value in this registe r. when the epafifocontrol register enfiford bit is set to 1, data can be read from the fifo by reading the value from this regist er. if a value is written in this register without setting the enfifowr bit, writing in the fifo is not executed. if a value is re ad from the register without setting the enfiford bit, dummy data is output. 7.2.61 57h epa fifo control (epafifocontrol) address register name r/w bit symbol description reset 57h epafifocontrol r 7: fifoempty 0: fifo not empty 1: fifo empty r 6: fifofull 0: fifo not full 1: fifo full 5: 0: 1: 4: 0: 1: 3: 0: 1: w 2: fifoclr 0: normal 1: fifo clear r/w 1: enfifowr 0: normal 1: enable fifo write r/w 0: enfiford 0: normal 1: enable fifo read 80h this register shows or controls the endpoint a fifo status. bit 7 fifoempty when this bit = 1, the fifo is empty. before reading data from the fifo, check to see that this bit = 0. bit 6 fifofull when this bit = 1, the fifo is full. before writing data into the fifo, check to see that this bit = 0. bit 5 reserved bit 4 reserved bit 3 reserved bit 2 fifoclr setting this bit to 1 clears the fifo. this bit is automatically cleared to 0 after the fifo is cleared. bit 1 enfifowr setting this bit to 1 allows data to be written into the fifo by the cpu. this bit cannot be set to 1 when the enfiford bit is 1. bit 0 enfiford setting this bit to 1 allows data to be read from the fifo by the cpu. this bit cannot be set to 1 when the enfifowr bit is 1.
S1R72003 technical manual 50 epson rev.1.0 7.2.62 58h epb config_0 (epbconfig_0) address register name r/w bit symbol description reset 58h epbconfig_0 r/w 7: inxout 0: out 1: in 6: 0: 1: 5: 0: 1: 4: 0: 1: 3: endpointnumber[3] 2: endpointnumber[2] 1: endpointnumber[1] r/w 0: endpointnumber[0] endpoint number 00h this register sets endpoint b. bit 7 inxout sets the transfer direction of the endpoint. 0: out direction 1: in direction bit 6 reserved bit 5 reserved bit 4 reserved bits 3-0 endpointnumber these bits set an endpoint number in the range from 01 to 15.
S1R72003 technical manual rev.1.0 epson 51 7.2.63 59h epb config_1 (epbconfig_1) address register name r/w bit symbol description reset 59h epbconfig_1 r/w 7: joinide 0: not join ide 1: join ide r/w 6: togglemode 0: 1: r/w 5: enendpoint 0: disable endpoint 1: enable endpoint r/w 4: doublebuf 0: single buffer 1: double buffer 3: 0: 1: 2: maxpacketsize[2] 1: maxpacketsize[1] r/w 0: maxpacketsize[0] max packet size 00h this register sets endpoint b. bit 7 joinide connects the endpoint to dma dma connects to the last endpoint that had this bit set to 1. immediately following the reset, the joinide bit is 0 for all endpoints. 0: do not connect this endpoint to dma. 1: connect this endpoint to dma. bit 6 togglemode sets the operation mode of the toggle bit (in transaction only). 0: toggle only when the transaction terminates normally. 1: always toggle for each transaction performed. bit 5 enendpoint setting this bit to 1 enables the endpoint. accesses to the endpoint are ignored when this bit = 0. set the appropriate value for this bit following a setconfiguration request from the host. 0: disables the endpoint. 1: enables the endpoint. bit 4 doublebuf setting this bit to 1 configures the fifo for the endpoint as double buffers. a memory space twice the size set by maxpacketsize is reserved in the fifo. 0: configure the fifo as a single buffer. 1: configure the fifo as double buffers. bit 3 reserved bits 2-0 maxpacketsize sets the maximum value of the packet size. the relationship between the set values and packet sizes is shown below. (bit 2, 1, 0) maxpacketsize fs hs 000 reserved reserved 001 8 bytes 8 bytes 010 16 bytes 16 bytes 011 32 bytes 32 bytes 100 64 bytes 64 bytes 101 512 bytes 110 111 reserved 1024 bytes the settings other than 512 bytes in the hs mode are used in interrupt transfers. use epc for isochronous transfer. after setting maxpacketsize and doublebuf for the endpoints, be sure to set the eprcontrol register allfifoclr bit to 1 to clear all fifos. in addition, ensure that the total fifo area reserved by endpoints a, b, c does not ex ceed 2432 bytes.
S1R72003 technical manual 52 epson rev.1.0 7.2.64 5ah epb control_0 (epbcontrol_0) address register name r/w bit symbol description reset 5ah epbcontrol_0 r/w 7: autoforcenak 0: normal 1: autoforcenak w 6: enshortpkt 0: normal 1: send short packet r/w 5: autoforcenakshort 0: normal 1: autoforcenakshort 4: 0: 1: 3: 0: 1: 2: 0: 1: r/w 1: forcenak 0: normal 1: forcenak r/w 0: forcestall 0: normal 1: forcestall 00h this register sets the operation of endpoint b. bit 7 autoforcenak this bit automatically sets the epbcontrol_0 register?s forcenak bit to 1 when the transaction completes normally. 0: do not automatically set forcenak bit. 1: automatically set forcenak bit. bit 6 enshortpkt(in transaction only) setting this bit to 1 allows the data in the current fifo to be transmitted as a short packet for an in transaction. this bit is automatically cleared to 0 when the packet transfer is finished. if this bit is set to 1 when no data exists in the fifo, a packet of zero length is transmitted in response to an in token from the host. bit 5 autoforcenakshort when this bit = 1, if the packet received during an out transaction that finished normally is a short packet, the forcenak bit is automatically set to 1. if the autoforcenak bit = 1, autoforcenak is given priority over this bit. 0: do not automatically set the forcenak bit to 1. 1: automatically set the forcenak bit to 1. bit 4 reserved bit 3 reserved bit 2 reserved bit 1 forcenak setting this bit to 1 makes a nak response to the transaction regardless of the data count and free sp ace in the fifo. if any transaction is currently underway and this bit was set a certain time after the transaction started, the bit setting takes effect in the subsequent transactions. bit 0 forcestall setting this bit to 1 causes the transaction to be responded by a stall. this bit is given priority over the forcenak bit. if a transaction is currently underway and this bit was set a certain time after the transaction started, the setting of this b it takes effect from the following transaction.
S1R72003 technical manual rev.1.0 epson 53 7.2.65 5bh epb control_1 (epbcontrol_1) address register name r/w bit symbol description reset 5bh epbcontrol_1 7: 0: 1: 6: 0: 1: 5: 0: 1: 4: 0: 1: r 3: togglestat toggle status 2: 0: 1: w 1: toggleset 0: normal 1: toggle set w 0: toggleclr 0: normal 1: toggle clear 00h this register indicates and controls the status of the endpoint b toggle bit. bit 7 reserved bit 6 reserved bit 5 reserved bit 4 reserved bit 3 togglestat indicates the status of the toggle sequence bit. bit 2 reserved bit 1 toggleset setting this bit to 1 sets the toggle sequence bit to 1. bit 0 toggleclr setting this bit to 1 clears the toggle sequence bit to 0. 7.2.66 5ch epb fifo remain high (epbfiforemain_h) address register name r/w bit symbol description reset 5ch epbfiforemain_h 7: epbfiforemaincounter[15] 6: epbfiforemaincounter[14] 5: epbfiforemaincounter[13] 4: epbfiforemaincounter[12] 3: epbfiforemaincounter[11] 2: epbfiforemaincounter[10] 1: epbfiforemaincounter[9] r 0: epbfiforemaincounter[8] endpoint b fifo remain counter high 00h this register shows the eight high-order bits that represent the remaining data counts in the endpoint b fifo. to acquire the fifo?s remaining data counts, access the epbfiforemain_h and epbfiforemain_l registers in pairs. be sure to access the epbfiforemain_h register first. 7.2.67 5dh epb fifo remain low (epbfiforemain_l) address register name r/w bit symbol description reset 5dh epbfiforemain_l 7: epbfiforemaincounter[7] 6: epbfiforemaincounter[6] 5: epbfiforemaincounter[5] 4: epbfiforemaincounter[4] 3: epbfiforemaincounter[3] 2: epbfiforemaincounter[2] 1: epbfiforemaincounter[1] r 0: epbfiforemaincounter[0] endpoint b fifo remain counter low 00h this register shows the eight low-order bits that represent the remaining data counts in the endpoint b fifo. to acquire the f ifo?s remaining data counts, access the epbfiforemain_h and epbfiforemain_l registers in pairs. be sure to access the epbfiforemain_h register first.
S1R72003 technical manual 54 epson rev.1.0 7.2.68 5eh epb fifo for cpu (epbfifoforcpu) address register name r/w bit symbol description reset 5eh epbfifoforcpu 7: epbfifodata[7] 6: epbfifodata[6] 5: epbfifodata[5] 4: epbfifodata[4] 3: epbfifodata[3] 2: epbfifodata[2] 1: epbfifodata[1] r/w 0: epbfifodata[0] endpoint b fifo access from cpu xxh this register is used for fifo access from the cpu. when the epbfifocontrol register enfifowr bit is set to 1, data can be written into the fifo by writing a value in this registe r. when the epbfifocontrol register enfiford bit is set to 1, data can be read from the fifo by reading the value from this regist er. if a value is written in this register without setting the enfifowr bit, writing in the fifo is not executed. if a value is re ad from the register without setting the enfiford bit, dummy data is output. 7.2.69 5fh epb fifo control (epbfifocontrol) address register name r/w bit symbol description reset 5fh epbfifocontrol r 7: fifoempty 0: fifo not empty 1: fifo empty r 6: fifofull 0: fifo not full 1: fifo full 5: 0: 1: 4: 0: 1: 3: 0: 1: w 2: fifoclr 0: normal 1: fifo clear r/w 1: enfifowr 0: normal 1: enable fifo write r/w 0: enfiford 0: normal 1: enable fifo read 80h this register shows or controls the endpoint b fifo status. bit 7 fifoempty when this bit = 1, the fifo is empty. before reading data from the fifo, check to see that this bit = 0. bit 6 fifofull when this bit = 1, the fifo is full. before writing data into the fifo, check to see that this bit = 0. bit 5 reserved bit 4 reserved bit 3 reserved bit 2 fifoclr setting this bit to 1 clears the fifo. this bit is automatically cleared to 0 after the fifo is cleared. bit 1 enfifowr setting this bit to 1 allows data to be written to the fifo by the cpu. this bit cannot be set to 1 when the enfiford bit is 1. bit 0 enfiford setting this bit to 1 allows data to be read from the fifo by the cpu. this bit cannot be set to 1 when the enfifowr bit is 1.
S1R72003 technical manual rev.1.0 epson 55 7.2.70 60h epc config_0 (epcconfig_0) address register name r/w bit symbol description reset 60h epcconfig_0 r/w 7: inxout 0: out 1: in 6: iso 0: normal 1: iso 5: 0: 1: 4: 0: 1: 3: endpointnumber[3] 2: endpointnumber[2] 1: endpointnumber[1] r/w 0: endpointnumber[0] endpoint number 00h this register sets endpoint c. bit 7 inxout sets the transfer direction of the endpoint. 0: out direction 1: in direction bit 6 iso setting this bit to 1 places the epc e ndpoint in isochronous mode. 0: use the endpoint for bulk or interrupt transfer 1: use the endpoint for isochronous transfer bit 5 reserved bit 4 reserved bits 3-0 endpointnumber these bits set an endpoint number in the range of 01 to 15.
S1R72003 technical manual 56 epson rev.1.0 7.2.71 61h epc config_1 (epcconfig_1) address register name r/w bit symbol description reset 61h epcconfig_1 r/w 7: joinide 0: not join ide 1: join ide r/w 6: togglemode 0: 1: r/w 5: enendpoint 0: disable endpoint 1: enable endpoint r/w 4: doublebuf 0: single buffer 1: double buffer 3: 0: 1: 2: maxpacketsize[2] 1: maxpacketsize[1] r/w 0: maxpacketsize[0] max packet size 00h this register sets endpoint c. bit 7 joinide connects the endpoint to dma. dma connects to the last endpoint that had this bit set to 1. immediately following the reset, the joinide bit is 0 for all endpoints. 0: do not connect this endpoint to dma. 1: connect this endpoint to dma. bit 6 togglemode sets the operation mode of the toggle bit (in transaction only). 0: toggle only when the transaction terminates normally. 1: always toggle for each transaction performed. bit 5 enendpoint setting this bit to 1 enables the endpoint. a ccesses to the endpoint are ignored when this bit = 0. set the appropriate value for this bit following a setconfiguration request from the host. 0: disables the endpoint. 1: enables the endpoint. bit 4 doublebuf setting this bit to 1 configures the fifo for the endpoint as double buffers. a memory space twice the size set by maxpacketsize is reserved in the fifo. 0: configure the fifo as a single buffer. 1: configure the fifo as double buffers. bit 3 reserved bits 2-0 maxpacketsize sets the maximum value of the packet size. the relationship between set values and packet sizes is shown below. (bit 2, 1, 0) maxpacketsize fs hs 000 reserved reserved 001 8 bytes 8 bytes 010 16 bytes 16 bytes 011 32 bytes 32 bytes 100 64 bytes 64 bytes 101 512 bytes 110 reserved reserved 111 reserved 1024 bytes the settings other than 512 bytes in the hs mode are used in interrupt transfers. for isochronous transfer, this type of transfer can be accomplished by setting the epcconfig_0 register iso bit to 1. in this case, the values set in the isomaxsize_h and isomaxsize_l registers are used for maxpacketsize, and the value set in maxpacketsize here is ignored. after setting maxpacketsize and doublebuf for the endpoints, be sure to set the eprcontrol register allfifoclr bit to 1 to clear all fifos. in addition, ensure that the total fifo area reserved by endpoints a, b, c does not ex ceed 2, 432 bytes.
S1R72003 technical manual rev.1.0 epson 57 7.2.72 62h epc control_0 (epccontrol_0) address register name r/w bit symbol description reset 62h epccontrol_0 r/w 7: autoforcenak 0: normal 1: autoforcenak w 6: enshortpkt 0: normal 1: send short packet r/w 5: autoforcenakshort 0: normal 1: autoforcenakshort 4: 0: 1: 3: 0: 1: 2: 0: 1: r/w 1: forcenak 0: normal 1: forcenak r/w 0: forcestall 0: normal 1: forcestall 00h this register sets the operation of endpoint c. bit 7 autoforcenak this bit automatically sets the epccontrol_0 register?s forcenak bit to 1 when the transaction completes normally. 0: do not automatically set forcenak bit. 1: automatically set forcenak bit. bit 6 enshortpkt(in transaction only) setting this bit to 1 allows the data in the current fifo to be transmitted as a short packet for an in transaction. this bit is automatically cleared to 0 when the packet transfer is finished. if this bit is set to 1 when no data exists in the fifo, a packet of zero length is transmitted in response to an in token from the host. bit 5 autoforcenakshort when this bit = 1, if the packet received during an out transaction that completes normally is a short packet, the forcenak bit is automatically set to 1. if the autoforcenak bit = 1, autoforcenak is given priority over this bit. 0: do not automatically set the forcenak bit to 1. 1: automatically set the forcenak bit to 1. bit 4 reserved bit 3 reserved bit 2 reserved bit 1 forcenak setting this bit to 1 makes a nak response to the transaction regardless of the data count and free sp ace in the fifo. if any transaction is currently underway and this bit was set a certain time after the transaction started, the bit setting takes effect in the subsequent transactions. bit 0 forcestall setting this bit to 1 causes the transaction to be responded by a stall. this bit is given priority over the forcenak bit. if a transaction is currently underway and this bit was set a certain time after the transaction started, the setting of this bit takes effect from the following transaction.
S1R72003 technical manual 58 epson rev.1.0 7.2.73 63h epc control_1 (epccontrol_1) address register name r/w bit symbol description reset 63h epccontrol_1 7: 0: 1: 6: 0: 1: 5: 0: 1: 4: 0: 1: r 3: togglestat toggle status 2: 0: 1: w 1: toggleset 0: normal 1: toggle set w 0: toggleclr 0: normal 1: toggle clear 00h this register indicates and controls the status of the endpoint c toggle bit. bit 7 reserved bit 6 reserved bit 5 reserved bit 4 reserved bit 3 togglestat indicates the status of the toggle sequence bit. bit 2 reserved bit 1 toggleset setting this bit to 1 sets the toggle sequence bit to 1. bit 0 toggleclr setting this bit to 1 clears the toggle sequence bit to 0. 7.2.74 64h epc fifo remain high (epcfiforemain_h) address register name r/w bit symbol description reset 64h epcfiforemain_h 7: epcfiforemaincounter[15] 6: epcfiforemaincounter[14] 5: epcfiforemaincounter[13] 4: epcfiforemaincounter[12] 3: epcfiforemaincounter[11] 2: epcfiforemaincounter[10] 1: epcfiforemaincounter[9] r 0: epcfiforemaincounter[8] endpoint c fifo remain counter high 00h this register shows the eight high-order bits that represent the remaining data counts in the endpoint c fifo. to acquire the fifo?s remaining data counts, access the epcfiforemain_h and epcfiforemain_l registers in pairs. be sure to access the epcfiforemain_h register first. 7.2.75 65h epc fifo remain low (epcfiforemain_l) address register name r/w bit symbol description reset 65h epcfiforemain_l 7: epcfiforemaincounter[7] 6: epcfiforemaincounter[6] 5: epcfiforemaincounter[5] 4: epcfiforemaincounter[4] 3: epcfiforemaincounter[3] 2: epcfiforemaincounter[2] 1: epcfiforemaincounter[1] r 0: epcfiforemaincounter[0] endpoint c fifo remain counter low 00h this register shows the eight low-order bits that represent the remaining data counts in the endpoint c fifo. to acquire the f ifo?s remaining data counts, access the epcfiforemain_h and epcfiforemain_l registers in pairs. be sure to access the epcfiforemain_h register first.
S1R72003 technical manual rev.1.0 epson 59 7.2.76 66h epc fifo for cpu (epcfifoforcpu) address register name r/w bit symbol description reset 66h epcfifoforcpu 7: epcfifodata[7] 6: epcfifodata[6] 5: epcfifodata[5] 4: epcfifodata[4] 3: epcfifodata[3] 2: epcfifodata[2] 1: epcfifodata[1] r/w 0: epcfifodata[0] endpoint c fifo access from cpu xxh this register is used for fifo access from the cpu. when the epcfifocontrol register enfifowr bit is set to 1, data can be written into the fifo by writing a value in this registe r. when the epcfifocontrol register enfiford bit is set to 1, data can be read from the fifo by reading the value from this regist er. if a value is written in this register without setting the enfifowr bit, writing in the fifo is not executed. if a value is re ad from the register without setting the enfiford bit, dummy data is output. 7.2.77 67h epc fifo control (epcfifocontrol) address register name r/w bit symbol description reset 67h epcfifocontrol r 7: fifoempty 0: fifo not empty 1: fifo empty r 6: fifofull 0: fifo not full 1: fifo full 5: 0: 1: 4: 0: 1: 3: 0: 1: w 2: fifoclr 0: normal 1: fifo clear r/w 1: enfifowr 0: normal 1: enable fifo write r/w 0: enfiford 0: normal 1: enable fifo read 80h this register shows or controls the endpoint c fifo status. bit 7 fifoempty when this bit = 1, the fifo is empty. before reading data from the fifo, check to see that this bit = 0. bit 6 fifofull when this bit = 1, the fifo is full. before writing data into the fifo, check to see that this bit = 0. bit 5 reserved bit 4 reserved bit 3 reserved bit 2 fifoclr setting this bit to 1 clears the fifo. this bit is automatically cleared to 0 after the fifo is cleared. bit 1 enfifowr setting this bit to 1 allows data to be written to the fifo by the cpu. this bit cannot be set to 1 when the enfiford bit is 1. bit 0 enfiford setting this bit to 1 allows data to be read from the fifo by the cpu. this bit cannot be set to 1 when the enfifowr bit is 1. 7.2.78 68h iso max packet size high (isomaxsize_h) address register name r/w bit symbol description reset 68h isomaxsize_h 7: 0: 1: 6: 0: 1: 5: 0: 1: 4: 0: 1: 3: 0: 1: 2: isomaxpacketsize[10] 1: isomaxpacketsize[9] r/w 0: isomaxpacketsize[8] isomaxpacketsize[10:8] 00h
S1R72003 technical manual 60 epson rev.1.0 7.2.79 69h iso max packet size low (isomaxsize_l) address register name r/w bit symbol description reset 69h isomaxsize_l 7: isomaxpacketsize[7] 6: isomaxpacketsize[6] 5: isomaxpacketsize[5] 4: isomaxpacketsize[4] 3: isomaxpacketsize[3] r/w 2: isomaxpacketsize[2] isomaxpacketsize[7:2] 1: 0: 1: 0: 0: 1: 00h when the transaction type of endpoint c is set to iso (the epcconfig_0.iso bit is set to 1), the epcconfig_1 register maxpacket size bit setting is ignored and the value set in this register becomes effective. set the maxpacketsize in units of 4 bytes. fs: 4 to 1,020 bytes hs: 4 to 1,024 bytes ensure that the total fifo area reserved by endpoints a, b, c does not ex ceed 2, 432 bytes. 7.2.80 6ah to 7fh reserved address register name r/w bit symbol description reset 6ah (reserved) 7: 0: 1: to 6: 0: 1: 7fh 5: 0: 1: 4: 0: 1: 3: 0: 1: 2: 0: 1: 1: 0: 1: 0: 0: 1: 00h 7.2.81 80h ide status (idestatus) address register name r/w bit symbol description reset 80h idestatus r 7: dmarq dmarq signal r 6: dmack dmack signal r 5: intrq intrq signal r 4: iordy iordy signal 3: 0: 1: 2: 0: 1: r 1: pdiag pdiag signal r 0: dasp dasp signal xxh this register indicates the status of the ide interface signals. bit 7 dmarq indicates the hdmarq signal status with positive logic. (reflects the value of the ide_config_1 register pdreqlevel bit.) bit 6 dmack indicates the xhdmack signal status with positive logic. bit 5 intrq indicates the hintrq signal status with positive logic. bit 4 iordy indicates the hiordy signal status with positive logic. bit 3 reserved bit 2 reserved bit 1 pdiag indicates the xhpdiag signal status with positive logic. bit 0 dasp indicates the xhdasp signal status with positive logic.
S1R72003 technical manual rev.1.0 epson 61 7.2.82 81h ide config_0 (ideconfig_0) address register name r/w bit symbol description reset 81h ideconfig_0 w 7: idebusreset 0: normal 1: ide bus reset 6: 0: 1: 5: 0: 1: 4: 0: 1: 3: 0: 1: r/w 2: notide 0: ide mode 1: port mode r/w 1: ultra 0: normal 1: ultra mode r/w 0: dma 0: normal 1: dma mode 00h this register sets the operation of the ide interface. bit 7 idebusreset setting this bit to 1 asserts the reset signal to the ide interface for a 50-s period. when this bit is read during assertion of xhreset, it indicates the value 1. if this bit is set again during assertion, xhreset is output for a 50-s period from that point in time. bit 6 reserved bit 5 reserved bit 4 reserved bit 3 reserved bit 2 notide this bit changes the minimum width of assert and negate pulses of strobe signals set by the ide_rmod and ide_tmod registers. when using the ide interface in the general-purpose dma mode, setting this bit to 1 reduces the minimum values of strobe signals, which can improve the transfer rate. note that when using the ide interface in the ide bus-compatible mode, setting this bit to 1 accepts set values out of the ide specifications. 0: assertpulsewidth in the ide_rmod and ide_tmod registers +5 x 16.6 ns (internal clock period 60 mhz) is set as an assert pulse width. negatepulsewidth in the ide_rmod and ide_tmod registers +3 x 16.6 ns (internal clock period 60 mhz) is set as a negate pulse width. 1: assertpulsewidth in the ide_rmod and ide_tmod registers +2 x 16.6 ns (internal clock period 60 mhz) is set as an assert pulse width. negatepulsewidth in the ide_rmod and ide_tmod registers +2 x 16.6 ns (internal clock period 60 mhz) is set as a negate pulse width. bit 1 ultra when the dma bit is set, this bit selects ultra-dma for the dma transfer mode. always use this bit along with the dma bit. setting this bit to 1 ignores the setting of the bus8 bit. 0: do not perform data transfer in ultra-dma mode. 1: perform data transfer in ultra-dma mode. bit 0 dma selects dma for transfer mode. unless this bit is set, transfers are performed in pio mode. 0: perform data transfer in pio mode. 1: perform data transfer in dma mode.
S1R72003 technical manual 62 epson rev.1.0 7.2.83 82h ide config_1 (ideconfig_1) address register name r/w bit symbol description reset 82h ideconfig_1 r/w 7: activeide 0: non-active ide 1: active ide r/w 6: delaystrobe 0: normal 1: delay strobe r/w 5: slave 0: master 1: slave r/w 4: interlock 0: normal 1: interlock r/w 3: pdreqlevel 0: active high 1: active low r/w 2: swap 0: normal 1: swap 1: 0: 1: r/w 0: bus8 0: bus16 1: bus8 00h this register sets the ide interface bus operations. bit 7 activeide following the reset, the ide interface by default has all of its pins set for the hi-z mode. setting this bit to 1 enables the ide (general-purpose dma). when this bit is set to 1, each pin switches to the i nput or output mode depending on how the slave bit is set. 0: disables the ide and portdma. 1: enables the ide and portdma. bit 6 delaystrobe setting this bit to 1 delays the strobe output by 2 from xhdmack during multiword dma. 0: do not delay the strobe output by 2 from xhdmack. 1: delay the strobe output by 2 from xhdmack. bit 5 slave determines the operation mode of the ide (general-purpose dma) interface unit. set this bit to 0 when using the ide interface in the ide bus-compatible mode. in the slave mode, the register functions from ide_rmod to ide_cs17 cannot be used. note that there is a delay time of 25 ns (typ) from xhior or xhiow assertion to hdmarq negation. 0: master mode (hdmarq functions as input; xhdmack, xhior, and xhiow function as output) 1: slave mode (hdmarq functions as output; xhdmack, xhior, and xhiow function as input) bit 4 interlock effective only in master dma mode. when this bit = 0, xhdmack is negated if the fifo becomes incapable of transfer. when this bit = 1, xhdmack is not negated even if the fifo becomes incapable of transfer. however, xhdmack is negated when hdmarq is dropped. 0: negate xhdmack. 1: do not negate xhdmack. bit 3 pdreqlevel determines the active level of the hdmarq signal. set this bit to 0 when using the ide interface as ide-like dma. 0: positive logic 1: negative logic bit 2 swap swaps the high-order and low-order 8 bits when using the ide interface at 16-bit width. the order in which the ide_cs00 register is accessed is also reversed. 0: transfer the low-order 8-bit data to the usb side first. 1: transfer the high-order 8-bit data to the usb side first. bit 1 reserved bit 0 bus8 set this bit to 1 when using the ide (general-purpose dma) interface with an 8-bit width. when this bit is set to 1, only the 8 low-order bits of the bus are valid. the 8 high-order bits are invalid. when using the ide interface at 8-bit width, 8 high-order bits must be fixed at high or low using pull-up/down resistors. clear this bit to 0 when using the ide interface in the ide bus-compatible mode. this bit is ignored if the ide_config_0 register ultra bit is set. 0: use the ide interface at 16-bit width. 1: use the ide interface at 8-bit width.
S1R72003 technical manual rev.1.0 epson 63 setting the port interface operations the following tables show the relationship between the operation modes set and the bit settings of this register (ide_config_1). when the port data bus is used as the ide interface, bits 5, 3, and 0 do not need to be set. the maximum delay time before hdmarq is negated in the slave mode is 37 ns, from the time at which xhiow or xhior is asserted to the time at which hdmarq is negated. slave/master switching of ports by the slave bit hdmarq xhdmack xhior / xhiow remarks slave = 0 (master) input output output data input during xhior (read) data output during xhiow (write) tmod settings effective xhior/ xhiow minimum pulse width: assertion >70 ns; negation >40 ns slave = 1 (slave) output input input data output during xhior (read) data input during xhiow (write) tmod settings have no effect. xhior/ xhiow minimum pulse assertion 25 ns negation 25 ns xhiow period 50 ns switching of operation modes by the bus8 and swap bits swap = 0 hdd7?0 is transferred first. the first data obtained by accessing ide_cs00 is hdd7?0. bus8 = 0 swap = 1 hdd15?8 is transferred first. the first data obtained by accessing ide_cs00 is hdd15?8. bus8 = 1 only hdd7?0 is used for transfer. hdd15?8 is in input mode. (these unused bits must be pulled high or low.) ide_cs00 is accessed for only hdd7?0. * the input/output delays depend on the magnitude of load of the connected device. the values shown above are derived by simulation assuming a load capacitance of 20 pf, with 10 ns margins added to each estimated value.
S1R72003 technical manual 64 epson rev.1.0 7.2.84 83h reserved address register name r/w bit symbol description reset 83h (reserved) 7: 0: 1: 6: 0: 1: 5: 0: 1: 4: 0: 1: 3: 0: 1: 2: 0: 1: 1: 0: 1: 0: 0: 1: 00h 7.2.85 84h ide register mode (ide_rmod) address register name r/w bit symbol description reset 84h ide_rmod 7: registerassertpulsewidth[3] 6: registerassertpulsewidth[2] 5: registerassertpulsewidth[1] r/w 4: registerassertpulsewidth[0] register assert pulse width 3:registernegatepulsewidth[3] 2:registernegatepulsewidth[2] 1:registernegatepulsewidth[1] r/w 0:registernegatepulsewidth[0] register negate pulse width 00h this register sets the access to the ide register area on the ide interface. bits 7-4 registerassertpulsewidth determine the minimum value of the period for which the strobe signal is asserted when accessing the register area of the ide interface. when the ide_config_0 register notide bit is 0, the setting is as follows: internal clock (60 mhz) period multiplied by (registerassertpulsewidth + 5) when the ide_config_0 register notide bit is 1, the setting is as follows: internal clock (60 mhz) period multiplied by (registerassertpulsewidth + 2) when the ide_config_0 register notide bit is 0, the setting is as follows: bits 3-0 registernegatepulsewidth determine the minimum value of the period for which the strobe signal is negated when accessing the register area of the ide interface. when the ide_config_0 register notide bit is 0, the setting is as follows: internal clock (60 mhz) period multiplied by (registernegatepulsewidth + 3) when the ide_config_0 register notide bit is 1, the setting is as follows: internal clock (60 mhz) period multiplied by (registernegatepulsewidth + 2) example: when the ide_config_0 register notide bit is 0: 00h: assertpulsewidth 16.6 ns (0000 + 5) = 83 ns and negatepulsewidth 16.6 ns (0000 + 3) = 49.8 ns 11h: assertpulsewidth 16.6 ns (0001 + 5) = 99.6 ns and negatepulsewidth 16.6 ns (0001 + 3) = 66.4 ns when the ide_config_0 register notide bit is 1: 00h: assertpulsewidth 16.6 ns (0000 + 2) = 33.2 ns and negatepulsewidth 16.6 ns (0000 + 2) = 33.2 ns 11h: assertpulsewidth 16.6 ns (0001 + 2) = 49.8 ns and negatepulsewidth 16.6 ns (0001 + 2) = 49.8 ns
S1R72003 technical manual rev.1.0 epson 65 7.2.86 85h ide transfer mode (ide_tmod) address register name r/w bit symbol description reset 85h ide_tmod 7: transferassertpulsewidth[3] 6: transferassertpulsewidth[2] 5: transferassertpulsewidth[1] r/w 4: transferassertpulsewidth[0] transfer assert pulse width 3:transfernegatepulsewidth[3] 2:transfernegatepulsewidth[2] 1:transfernegatepulsewidth[1] r/w 0:transfernegatepulsewidth[0] transfer negate pulse width 00h this register sets the manner in which data transfers are performed via the ide interface. bits 7-4 transferassertpulsewidth determine the minimum value of the period for which the strobe signal is asserted when performing data transfers via the ide interface. when the ide_config_0 register notide bit is 0, the setting is as follows: internal clock (60 mhz) period multiplied by (transferassertpulsewidth + 5) when the ide_config_0 register notide bit is 1, the setting is as follows: internal clock (60 mhz) period multiplied by (transferassertpulsewidth + 2) bits 3-0 transfernegatepulsewidth determine the minimum value of the period for which the strobe signal is negated when performing data transfers via the ide interface. when the ide_config_0 register notide bit is 0, the setting is as follows: internal clock (60 mhz) period multiplied by (transfernegatepulsewidth + 3) when the ide_config_0 register notide bit is 1, the setting is as follows: internal clock (60 mhz) period multiplied by (transfernegatepulsewidth + 2) example: when the ide_config_0 register notide bit is 0: 00h: assertpulsewidth 16.6 ns (0000 + 5) = 83 ns and negatepulsewidth 16.6 ns (0000 + 3) = 49.8 ns 11h: assertpulsewidth 16.6 ns (0001 + 5) = 99.6 ns and negatepulsewidth 16.6 ns (0001 + 3) = 66.4 ns when the ide_config_0 register notide bit is 1: 00h: assertpulsewidth 16.6 ns (0000 + 2) = 33.2 ns and negatepulsewidth 16.6 ns (0000 + 2) = 33.2 ns 11h: assertpulsewidth 16.6 ns (0001 + 2) = 49.8 ns and negatepulsewidth 16.6 ns (0001 + 2) = 49.8 ns 7.2.87 86h ide ultra-dma transfer mode (ide_umod) address register name r/w bit symbol description reset 86h ide_umod 7: 0: 1: 6: 0: 1: 5: 0: 1: 4: 0: 1: 3: ultradmacycle[3] 2: ultradmacycle[2] 1: ultradmacycle[1] r/w 0: ultradmacycle[0] ultra dma cycle 00h this register sets the minimum cycle time of the strobe signal when performing data transfers in ultra-dma mode via the ide interface. bit 7 reserved bit 6 reserved bit 5 reserved bit 4 reserved bits 3-0 ultradmacycle determine the minimum cycle time of the strobe signal when performing data transfers in ultra-dma mode via the ide interface. this is the internal clock (60 mhz) period multiplied by (ultradmacycle + 2). example: if these bits are set to ?00h,? then ultradmacycle = 16.6 ns (0000 + 2) = 33.2 ns if these bits are set to ?01h,? then ultradmacycle = 16.6 ns (0001 + 2) = 49.8 ns
S1R72003 technical manual 66 epson rev.1.0 7.2.88 87h reserved address register name r/w bit symbol description reset 87h (reserved) 7: 0: 1: 6: 0: 1: 5: 0: 1: 4: 0: 1: 3: 0: 1: 2: 0: 1: 1: 0: 1: 0: 0: 1: 00h 7.2.89 88h ide control_0 (idecontrol_0) address register name r/w bit symbol description reset 88h idecontrol_0 w 7: ideflush 0: normal 1: ide flush w 6: idefclr 0: normal 1: ide fifo clear 5: 0: 1: 4: 0: 1: 3: 0: 1: 2: 0: 1: 1: 0: 1: r/w 0: dtgo 0: dma transfer stop 1: dma transfer go 00h this register controls the ide during transfer operations. bit 7 ideflush setting this bit to 1 terminates (or temporarily stops) the dma transfer. when the dma transfer is stopped, the dtgo bit is cleared to 0 and the ideintstat register dtcmp bit is set to 1. by using this bit, dma transfer can be stopped and restarted without causing loss of data. to restart the transfer, check that the dtgo bit is cleared to 0 (or wait until the dma transfer stops), set a transfer count in the ide_count register, and set the dtgo bit to 1 again. the use of this bit to stop the transfer during dma reception bit may cause loss of data. the period from the moment at which this bit is set to 1 to the moment at which the dma transfer stops (the dtgo bit is cleared to 0) is the period necessary for 32-word (max.) data transfer in ultra dma transfer or 8-byte data (max.) transfer in the other dma transfer modes. 0: perform no operation. 1: stop dma transfer. bit 6 idefclr even if the other party to the dma transfer aborts the operation by clearing dtgo to 0 while dmarq it asserted remains active, dmack is not negated. however, in such cases, setting this bit to 1 can forcibly negate dmack. before setting this bit to 1, wait until the clock counts set by idetmod expire after clearing dtgo to 0. bit 5 reserved bit 4 reserved bit 3 reserved bit 2 reserved bit 1 reserved bit 0 dtgo setting this bit to 1 starts dma transfer. this bit is automatically cleared to 0 when the dma transfer is finished. setting this bit to 0 during dma transfer forcibly terminates the transfer (the bit is cleared to 0 when the dma transfer stops). note that, however, forcible termination of dma transfer may cause loss of data. when the dma transfer is stopped, the ideintstat register dtcmp bit is set to 1. the period from the moment at which this bit is set to 0 to the moment at which the dma transfer stops is the period necessary for 32-word (max.) data transfer in ultra dma transfer or 8-byte data (max.) transfer in the other dma transfer modes. 0: stop dma transfer. 1: start dma transfer.
S1R72003 technical manual rev.1.0 epson 67 7.2.90 89h reserved address register name r/w bit symbol description reset 89h (reserved) 7: 0: 1: 6: 0: 1: 5: 0: 1: 4: 0: 1: 3: 0: 1: 2: 0: 1: 1: 0: 1: 0: 0: 1: 00h 7.2.91 8ah ide transfer byte count high (ide_count_h) address register name r/w bit symbol description reset 8ah ide_count_h 7: ide_count[23] 6: ide_count[22] 5: ide_count[21] 4: ide_count[20] 3: ide_count[19] 2: ide_count[18] 1: ide_count[17] r/w 0: ide_count[16] ide count high 00h this register sets the 23rd to 16th bits of the transfer byte count in dma transfer. after the transfer is started by setting the ide_control_0 register dtgo bit, read this register to determine the value in the 23rd to 16th bits (high count value) of the remaining transfer byte count. to determine the full byte count that remains to be transferred, access registers ide_c ount_h, ide_count_m, and ide_count_l, in that order. 7.2.92 8bh ide transfer byte count middle (ide_count_m) address register name r/w bit symbol description reset 8bh ide_count_m 7: ide_count[15] 6: ide_count[14] 5: ide_count[13] 4: ide_count[12] 3: ide_count[11] 2: ide_count[10] 1: ide_count[9] r/w 0: ide_count[8] ide count middle 00h this register sets the 15th to 8th bits of the transfer byte count in dma transfer. after the transfer is started by setting t he ide_control_0 register dtgo bit, read this register to determine the value in the 15th to 8th (middle count value) of the remai ning transfer byte count. to determine the full byte count that remains to be transferred, access registers ide_c ount_h, ide_count_m, and ide_count_l, in that order. 7.2.93 8ch ide transfer byte count low (ide_count_l) address register name r/w bit symbol description reset 8ch ide_count_l 7: ide_count[7] 6: ide_count[6] 5: ide_count[5] 4: ide_count[4] 3: ide_count[3] 2: ide_count[2] 1: ide_count[1] r/w 0: ide_count[0] ide count low 00h this register sets the 7th to 0th bits of the transfer byte count in dma transfer. after the transfer is started by setting th e ide_control_0 register dtgo bit, read this register to determine the value in the 7th to 0th (low count value) of the remaining transfer byte count. to determine the full byte count that remains to be transferred, access registers ide_c ount_h, ide_count_m, and ide_count_l, in that order.
S1R72003 technical manual 68 epson rev.1.0 7.2.94 8dh ide crc control (ide_crccontrol) address register name r/w bit symbol description reset 8dh ide_crccontrol 7: 0: 1: 6: 0: 1: 5: 0: 1: 4: 0: 1: 3: 0: 1: 2: 0: 1: 1: 0: 1: w 0: clear 0: normal 1: ide crc clear 00h this register controls crc during ultra-dma transfer by ide. bit 7 reserved bit 6 reserved bit 5 reserved bit 4 reserved bit 3 reserved bit 2 reserved bit 1 reserved bit 0 clear setting this bit to 1 initializes the internal crc calculation circuit during ultra-dma transfer. this bit is write-only, and is automatically cleared to 0 by completion of initialization. at dma startup, this circuit is automatically initialized by the internal logic. 7.2.95 8eh ide crc high (ide_crc_h) address register name r/w bit symbol description reset 8eh ide_crc_h 7: crc[15] 6: crc[14] 5: crc[13] 4: crc[12] 3: crc[11] 2: crc[10] 1: crc[9] r 0: crc[8] crc high 4ah this register shows the 8 high-order bits of the result of the crc calculation made when performing data transfers in ultra-dma mode via the ide interface. to acquire the crc value of the ide, access the ide_crc_h and ide_crc_l registers in pairs. be sure to access the ide_crc_h register first. 7.2.96 8fh ide crc low (ide_crc_l) address register name r/w bit symbol description reset 8fh ide_crc_l 7: crc[7] 6: crc[6] 5: crc[5] 4: crc[4] 3: crc[3] 2: crc[2] 1: crc[1] r 0: crc[0] crc low bah this register shows the 8 low-order bits of the result of the crc calculation made when performing data transfers in ultra-dma mode via the ide interface. to acquire the crc value of the ide, access the ide_crc_h and ide_crc_l registers in pairs. be sure to access the ide_crc_h register first.
S1R72003 technical manual rev.1.0 epson 69 7.2.97 90h ide_cs00 (ide_cs00) address register name r/w bit symbol description reset 90h ide_cs00 7: ide_cs00[7] 6: ide_cs00[6] 5: ide_cs00[5] 4: ide_cs00[4] 3: ide_cs00[3] 2: ide_cs00[2] 1: ide_cs00[1] r/w 0: ide_cs00[0] ide cs00 xxh this register shows the area accessed by the cpu as it accesses the ide interface data ports. the transfer mode is set to pio mode, and the access is made under the conditions set in the ide_tmod register. the settings for the ide_config_1 register?s bus8 and swap bits are reflected in the accesses performed here. thus, for 16-bit wide operations, the ide bus can be accessed in 16 bits by always accessing this register twice. for 8-bit wide operations, th e ide bus can be accessed in a single operation. accessing the ide_cs00 register during dma transfer is inhibited.
S1R72003 technical manual 70 epson rev.1.0 7.2.98 91h to 9fh ide_cs01 to ide_cs17 (ide_cs01 to ide_cs17) address register name r/w bit symbol description reset 91h ide_cs01 7: ide_csxx[7] to to 6: ide_csxx[6] 9fh ide_cs17 5: ide_csxx[5] 4: ide_csxx[4] 3: ide_csxx[3] 2: ide_csxx[2] 1: ide_csxx[1] r/w 0: ide_csxx[0] ide csxx xxh these registers show the areas that are accessed by the cpu as it accesses the ide interface register area. the transfer mode is set to pio mode, and the access is made under the conditions set in the ide_rmod register. transfers are performed at a fixed length of 8 bits, using the bus signals dd7?0. for accesses of registers ide_cs01 through ide_cs17 during dma transfer, if the ide_config_1 register interlock bit in dma mode is 0, xhdmack is temporarily negated before the cpu makes the access. however, during ultra-dma transfers, or if the interlock bit = 1, the cpu cannot perform the access until xhdmack is negated (when hdmarq is dr opped) or the transfer is complete. the contents of each register in ide operations are shown below: ide_cs01 read: shows the ata error register. write: shows the ata features register. ide_cs02 shows the ata sector count register. ide_cs03 shows the ata sector number register. ide_cs04 shows the ata cylinder low register. ide_cs05 shows the ata cylinder high register. ide_cs06 shows the ata device/head register. ide_cs07 read: shows the ata status register. write: shows the ata command register. ide_cs10 ide_cs11 ide_cs12 ide_cs13 ide_cs14 ide_cs15 ide_cs16 read: shows the ata alternate status register. write: shows the ata device control register. ide_cs17
S1R72003 technical manual rev.1.0 epson 71 7.2.99 a0h to beh cbw_00 to csw_30 (cbw_00 to cbw_30) address register name r/w bit symbol description reset a0h cbw_00 7: cbw_xx[7] to to 6: cbw_xx[6] beh cbw_30 5: cbw_xx[5] 4: cbw_xx[4] 3: cbw_xx[3] 2: cbw_xx[2] 1: cbw_xx[1] r/w 0: cbw_xx[0] bulk out received cbw data xxh these registers are used in the usb storage-class bulkonly transport protocol. when the bulkonlycontrol register gocbwmode bit = 1 and valid cbw data is received at the set bulk out e ndpoint, the bulkintstat register?s cbwcmp interrupt is generated, and the received cbw data is stored in these registers. if a cbwshort, cbwlong, or cbwerr interrupt occurs, the contents of these registers are invalid. if a cbwcmp, cbwshort, or cbwlong interrupt occurs, the bulkonlycontrol register gocbwmode bit is automatically cleared to 0. however, when a cbwerr interrupt occurs, the gocbwmode bit is not automatically cleared. these registers can be accessed only when the gocbwmode bit = 0. 7.2.100 bfh reserved address register name r/w bit symbol description reset bfh (reserved) 7: 0: 1: 6: 0: 1: 5: 0: 1: 4: 0: 1: 3: 0: 1: 2: 0: 1: 1: 0: 1: 0: 0: 1: 00h 7.2.101 c0h to cch csw0_00 to csw0_12 (csw0_00 to csw0_12) address register name r/w bit symbol description reset c0h csw0_00 7: csw0_xx[7] to to 6: csw0_xx[6] cch csw0_12 5: csw0_xx[5] 4: csw0_xx[4] 3: csw0_xx[3] 2: csw0_xx[2] 1: csw0_xx[1] r/w 0: csw0_xx[0] bulk in transfer csw0 data xxh these registers are used in the usb storage-class bulkonly transport protocol. when the bulkonlycontrol register gocswmode bit = 1, if the set bulk in endpoint has a csw transmit request and the bulkonlycontrol register cswsel bit = 0, the contents of the csw0_00 to csw0_12 registers are transmitted. the bulkintstat register?s cswcmp or cswerr interrupt is generated after transmitting the csw. when a cswcmp interrupt occurs, the gocswmode bit is cleared to 0 and the gocbwmode bit is set to 1. when a cswerr interrupt occurs, however, neither the gocswmode bit is cleared, nor is the gocbwmode bit set. these registers can be accessed only when the gocswmode bit = 0.
S1R72003 technical manual 72 epson rev.1.0 7.2.102 cdh to cfh reserved address register name r/w bit symbol description reset cdh (reserved) 7: 0: 1: to 6: 0: 1: cfh 5: 0: 1: 4: 0: 1: 3: 0: 1: 2: 0: 1: 1: 0: 1: 0: 0: 1: 00h 7.2.103 d0h to dch csw1_00 to csw1_12 (csw1_00 to csw1_12) address register name r/w bit symbol description reset d0h csw1_00 7: csw1_xx[7] to to 6: csw1_xx[6] dch csw1_12 5: csw1_xx[5] 4: csw1_xx[4] 3: csw1_xx[3] 2: csw1_xx[2] 1: csw1_xx[1] r/w 0: csw1_xx[0] bulk in transfer csw1 data xxh these registers are used in the usb storage-class bulkonly transport protocol. when the bulkonlycontrol register gocswmode bit = 1, if the set bulk in endpoint has a csw transmit request and the bulkonlycontrol register cswsel bit = 1, the contents of the csw1_00 through csw1_12 registers are transmitted. the bulkintstat register?s cswcmp or cswerr interrupt is generated after transmitting the csw. when a cswcmp interrupt occurs, the gocswmode bit is cleared to 0 and the gocbwmode bit is set to 1. however, when a cswerr interrupt occurs, however, neither the gocswmode bit is cleared, nor is the gocbwmode bit set. these registers can be accessed only when the gocswmode bit = 0. 7.2.104 ddh to dfh reserved address register name r/w bit symbol description reset ddh (reserved) 7: 0: 1: to 6: 0: 1: dfh 5: 0: 1: 4: 0: 1: 3: 0: 1: 2: 0: 1: 1: 0: 1: 0: 0: 1: xxh
S1R72003 technical manual rev.1.0 epson 73 7.2.105 e0h port direction (portdir) address register name r/w bit symbol description reset e0h portdir 7: 0: 1: 6: 0: 1: 5: 0: 1: 4: 0: 1: 3: 0: 1: 2: 0: 1: r/w 1: portdir1 0: input 1: output r/w 0: portdir0 0: input 1: output 00h this register sets the input/output direction of each bit for general-purpose io ports. the ports can be set for i nput or output modes bitwise. when reset, the direction of each bit is set for i nput by default. this register is effective even during snooze. 0: input mode 1: output mode bit 7 reserved bit 6 reserved bit 5 reserved bit 4 reserved bit 3 reserved bit 2 reserved bit 1 portdir1 sets the input/output direction of port1. bit 0 portdir0 sets the input/output direction of port0. 7.2.106 e1h port data (portdata) address register name r/w bit symbol description reset e1h portdata 7: 0: 1: 6: 0: 1: 5: 0: 1: 4: 0: 1: 3: 0: 1: 2: 0: 1: r/w 1: portdata1 port1 data r/w 0: portdata0 port0 data xxh this register sets or acquires the status of general-purpose i/o ports. writes to bits set for input mode are ignored. this register is effective even during snooze. bit 7 reserved bit 6 reserved bit 5 reserved bit 4 reserved bit 3 reserved bit 2 reserved bit 1 portdata1 sets or acquires the status of port1. bit 0 portdata0 sets or acquires the status of port0.
S1R72003 technical manual 74 epson rev.1.0 8. typical connections 8.1 example of connecting usb interface and other pins ? use 45 ? wiring impedance for the dp/dm lines. (45 ? between dp and gnd, 45 ? between dm and gnd, and 90 ? between dp and dm) ? make sure the dp/dm lines have the same in lengths and are wired over the shortest possible distance. ? connect r1 (pin 1) to av ss (pin 5) via a 6 k ? 5% resistor. make sure the r1 pin and the resistor are wired over the shortest possible distance. ? for xi (pin 99) and xo (pin 100), refer to the example connection for the crystal resonator. (shown above is an example for 12 mhz oscillation; clksel0,1 = ?00?) ? connect xv dd (pin 91) to xv ss (pin 90) by inserting a 0.1 f (ceramic capacitor) and a 10 to 22 f (tantalum or aluminum electrolytic capacitor) on the xv dd side. ? connect pv dd (pin 93) to pv ss (pin 95) by inserting a 0.1 f (ceramic capacitor) on the pv dd side. also, connect gnd for xi and xo in the vicinity of pv ss to stabilize crystal oscillator circuit operation. ? connect av dd on pin 4 to av ss on pin 5 by inserting a 0.1 f (ceramic capacitor) and a 10 to 22 f (tantalum or aluminum electrolytic capacitor) on the av dd side. connect av dd on pins 6 and 12 to av ss on pins 7 and 11 by inserting a 0.1 f (ceramic capacitor) on the av dd side, respectively. connect av dd on pins 6 and 12 to av ss on pin 9 by inserting a 0.1 f (ceramic capacitor) on the av dd side. make sure the capacitors inserted for pins 6, 7, 9, 11, and 12 are positioned symmetrically, centering on pin 9 . 90 xv ss 91 xv dd 93 pv dd 95 pv ss 96 vc 97 ptest 99 xi 100 xo 1 r1 4 av dd 5 av ss 6 av dd 7 av ss 8 dp 9 av ss 10 dm 11 av ss 12 av dd 22 + 6.2k 1% 1 m 0.1 24p 24p 0.1 12mhz pv ss v ss pv ss pv dd xv dd xv ss 0.1 av ss av ss 14 vbus v ss 10k 13 tsten 88 clksel1 87 clksel0 0.1 0.1 av ss 0.1 0.1 av ss 22 220 v ss + + av ss to usb connector dp,dm,v cc S1R72003 av dd av dd av dd
S1R72003 technical manual rev.1.0 epson 75 8.2 example of connecting ide interface and other pins 33 v ss 40 gnd 39 dasp 38 cs1 37 cs0 v ss 75 v dd 76 hiordy 74 xhior 73 xhiow 72 hdmarq 71 v dd 70 hdd15 69 hdd0 68 hdd14 67 hdd1 66 hdd13 65 hdd2 64 hdd12 63 hdd3 62 v ss 61 hdd11 60 hdd4 59 hdd10 58 hdd5 57 hdd9 56 hdd6 55 hdd8 54 hdd7 53 xhreset 52 v dd 51 xdmack 77 hintrq 78 hda1 79 xhpdiag 80 hda0 81 hda2 82 xhcs0 83 xhcs1 84 xhdasp 85 v ss 86 36 da2 35 da0 34 pdiag 33 da1 32 nc 31 intrq 30 gnd 29 dmack 28 csel 27 iordy 26 gnd 25 dior 24 gnd 23 diow 22 gnd 21 dmarq 20 nc 19 gnd 18 dd15 17 dd0 16 dd14 15 dd1 14 dd13 13 dd2 12 dd12 11 dd3 10 dd11 9 dd4 8 dd10 7 dd5 6 dd9 5 dd6 4 dd8 3 dd7 2 gnd 1 reset 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 82 22 22 82 82 22 33 33 33 33 33 4.7k v ss 10k 10k 5.6k 5v v dd v ss 50 v ss 10 0.1 + 0.1 v ss 0.1 v ss v ss S1R72003 ide connector v dd v dd
S1R72003 technical manual 76 epson rev.1.0 8.3 examples of connection of ide i/f pins (when general-purpose dma is used) v ss 75 v dd 76 hiordy 74 xhior 73 xhiow 72 hdmarq 71 v dd 70 hdd15 69 hdd0 68 hdd14 67 hdd1 66 hdd13 65 hdd2 64 hdd12 63 hdd3 62 v ss 61 hdd11 60 hdd4 59 hdd10 58 hdd5 57 hdd9 56 hdd6 55 hdd8 54 hdd7 53 xhreset 52 v dd 51 xdmack 77 hintrq 78 hda1 79 xhpdiag 80 hda0 81 hda2 82 xhcs0 83 xhcs1 84 xhdasp 85 v ss 86 acknowledge signal read/write strobe signal * 2 request signal data bus * 1 v dd v ss 50 v ss 10 0.1 + 0.1 v ss 0.1 v ss v ss S1R72003 dma i/f v dd v dd * 1 . processing, such as pull up/pull down, may be required according to a device to be connected so that hi-z cannot be input. * 2. the connection method slightly differs according to a device to be connected and system configuration. see the examples of connection of appended table 1. * 3. unused output pin. no problem due to open. 10k v dd 10k v dd v ss 10k v dd * 3 when dma transfer is performed between S1R72003 and the other device S1R72003 xhior xhiow other dev read strobe write strobe memory read strobe write strobe S1R72003 xhior xhiow dmac read strobe write strobe when dma transfer is performed between S1R72003 and the memory using an external dmac (master) examples of connection appended table 1
S1R72003 technical manual rev.1.0 epson 77 8.4 example of connecting cpu interface and other pins external clock input pinexternal clock input pin 10k 1000p 10k 5v v ss external clock input pin oscout 49 v ss 48 tin1 47 tin0 46 tport1 45 tport0 44 scanen 43 atpgen 42 v dd 41 cd7 40 cd6 39 cd5 38 cd4 37 vss 36 cd3 35 cd2 34 cd1 33 cd0 32 xint 31 xwr 30 xwait 29 xrd 28 xcs 27 v dd 26 v ss 25 v ss 0.1 0.1 v ss 24 ca7 23 ca6 22 ca5 21 ca4 20 ca3 19 ca2 18 ca1 17 ca0 16 xsleep 15 xreset v ss v ss data input/output pins external interrupt input pin write strobe output pin wait input pin read strobe output pin chip select output pin address output pins S1R72003 cpu system reset system sleep external pin the cpu in this example operates at a 5 v power supply and requires a level shift circuit like the one shown here. depending on the cpu's dc characteristics, a more precise level shift circuit may be needed. * 1. *1. 10k 10k v dd v dd v dd v dd
S1R72003 technical manual 78 epson rev.1.0 9. electrical characteristics 9.1 absolute maximum ratings (v ss = 0 v) parameter symbol rated value unit power supply voltage v dd -0.3 to +4.0 v input voltage v i -0.3 to v dd + 0.5 *1 v output voltage v o -0.3 to v dd + 0.5 *1 v output current per pin i out 30 ma power supply current i ddl 300 ma storage temperature t stg -65 to +150 c *1: for the pins shown in appended table 1, the specification value can be used from -0.3 to 7.0 v. appended table 1 pin name xreset, xsleep, ca[7:0], cd[7:0], xcs, xrd, xwr, hdd[15:0], xhior xhiow, hdmarq, xhdmack, hiordy, hintrq, xhdasp, xhdiag, vbus 9.2 recommended operating conditions parameter symbol min. typ. max. unit power supply voltage v dd 3.0 3.3 3.6 v input voltage v i v ss - v dd * 1 v ambient temperature ta 0 25 70 c *1: for the pins shown in appended table 1, the specification value can be used up to 5.25 v. however, for the pins shown in appended table 2, the pull up exceeding v dd can be used. appended table 2 pin name cd[7:0], hdd[15:0], xhior, xhiow, hdmarq, xhdmack
S1R72003 technical manual rev.1.0 epson 79 9.3 dc characteristics input characteristics in dc state (under recommended operating conditions) parameter symbol test condition min. typ. max. unit power supply source current power supply current * 1 i ddh v dd = 3.3 v - - 150 ma quiescent current v in = v dd or v ss power supply current i dds v dd = 3.6 v - - 90 a input leakage v in = v dd or v ss input leakage current i l v dd = 3.6 v -1 - 1 a input characteristics (cmos) pin names: tsten, xsleep, ca7..ca0, cd7..cd0, xcs, xrd xwr, hdd15..hdd0, xhior, xhiow, hdmarq, xhdmack high level input voltage v ih1 v dd = 3.6 v 2.0 - - v low level input voltage v il1 v dd = 3.0 v - - 0.8 v input characteristics (ttl) pin names: scanen, atpgen, tin1, tin0, clksel1, clksel0 high level input voltage v ih2 v dd = 3.6 v 2.0 - - v low level input voltage v il2 v dd = 3.0 v - - 0.8 v schmitt input characteristics(ttl) pin names: xreset, hiordy, hintrq, xhdasp, xhpdiag, tport1, tport0, vbus high level trigger voltage v t1+ v dd = 3.6 v 1.1 - 2.4 v low level trigger voltage v t1- v dd = 3.0 v 0.6 - 1.8 v hysteresis voltage ? v v dd = 3.0 v 0.1 - - v schmitt input characteristics (usb: fs) pin names: dp, dm high level trigger voltage v t+(usb) v dd = 3.6 v 1.1 - 1.8 v low level trigger voltage v t-(usb) v dd = 3.0 v 1.0 - 1.5 v hysteresis voltage ? v (usb) v dd = 3.0 v 0.1 - - v input characteristics (usb: fs differential input) pin names: dp and dm in pairs v dd = 3.0 v differential input voltage differential input sensitivity v ds(usb) 0.8 v to 2.5 v - - 0.2 v input pulldown characteristics pin names: tsten v dd = 3.3 v pulldown resistance value r pld1 v ih = v dd 20 50 100 k ? input pulldown characteristics pin names: scanen, atpgen, tin1, tin0 v dd = 3.3 v pulldown resistance value r pld2 v ih = v dd 40 100 200 k ? input pullup characteristics pin names: xsleep, ca7..ca0, cd7..cd0, xcs, xrd, xwr, v dd = 3.0 v pullup resistance value r plu2 v ih = v ss 40 100 200 k ?
S1R72003 technical manual 80 epson rev.1.0 output characteristics in dc state (under recommended operating conditions) parameter symbol test condition min. typ. max. unit output characteristics pin names: tport1, tport0 v dd = 3.0 v high level output voltage v oh1 i oh = -2 ma v dd -0.4 - - v v dd = 3.0 v low level output voltage v ol1 i ol = 2 ma - - 0.4 v output characteristics pin names: cd7..cd0, xwait, xint, hdd15..hdd0, hda2..hda0, xhcs1, xhcs0, xhior xhiow, hdmarq, xhdmack, xhreset v dd = 3.0 v high level output voltage v oh2 i oh = -6 ma v dd ?0.4 - - v v dd = 3.0 v low level output voltage v ol2 i ol = 6 ma - - 0.4 v output characteristics (usb: fs) pin names: dp, dm high level output voltage v oh(usb) v dd = 3.0 v 2.8 - - v low level output voltage v ol(usb) v dd = 3.6 v - - 0.3 v output characteristics (usb: hs) pin names: dp, dm high level output voltage v hsoh(usb) v dd = 3.0 v 360 - - mv low level output voltage v hsol(usb) v dd = 3.6 v - - 10.0 mv output characteristics pin names: all output pins v dd = 3.6 v v oh = v dd off state leakage current i oz v ol = v ss -1 - 1 a pin capacitance pin names: all input pins f = 1 mhz input pin capacitance c i v dd = v ss - - 10 pf pin capacitance pin names: all output pins f = 1 mhz output pin capacitance c o v dd = v ss - - 10 pf pin capacitance pin names: all input/output pins f = 1 mhz input/output pin capacitance c io v dd = v ss - - 10 pf *1 : it is current at the time of operation by recommendation operation conditions (typ.:v dd =3.3v and ta = 25 c).
S1R72003 technical manual rev.1.0 epson 81 9.4 ac characteristics 9.4.1 cpu i/f access timing 9.4.1.1 read timing symbol description min. max. unit t 201 one read cycle time 100 - ns t 202 ca, xcs setup time relative to xrd 2 - ns t 203 ca hold time relative to xrd 2 - ns t 204 xwait assert time relative to xcs - 10 ns t 205 cd output delay time relative to xrd - 20 ns t 206 cd output delay time relative to xwait - 5 ns t 207 xrd negate time relative to xwait 10 - ns * t 208 read data hold time relative to xrd or xcs 2 - ns t 209 hold time from xrd to the next xrd or xwr 20 - ns * t 208 is the data hold time relative to the rising edge of xrd or xcs, whichever goes high first. ca[7:0] xcs xrd cd[7:0] valid t 202 t 204 t 201 t 208 t 209 xwr t 203 xwait(wait mode) xwait(ready mode) t 206 t 205 t 207
S1R72003 technical manual 82 epson rev.1.0 9.4.1.2 write timing symbol description min. max. unit t 211 one write cycle time 100 - ns t 212 ca, xcs setup time relative to xwr 2 - ns t 213 ca hold time relative to xwr 2 - ns t 214 xwait assert time relative to xcs - 10 ns t 215 xwait assert time relative to xcs 10 - ns * t 216 write data setup time relative to xwr or xcs 10 - ns * t 217 write data hold time relative to xwr or xcs 5 - ns t 218 hold time from xwr to the next xrd or xwr 20 - ns * t 216 and t 217 are the data setup and hold times relative to the rising edge of xwr or xcs, whichever goes high first. ca[7:0] xcs xwr cd[7:0] stable t 212 t 215 t 213 t 218 xrd t 211 xwait(wait mode) xwait(ready mode) t 214 t 216 t 217
S1R72003 technical manual rev.1.0 epson 83 9.4.2 ide i/f timing 9.4.2.1 pio read timing symbol description min. typ. max. unit t 321 xhcs0 hda hda output delay time - 0 - ns t 322 xhcs0 hda hda hold time - 0 - ns t 323 xhcs0 xhior xhcs0 setup time 60 - - ns t 324 xhior xhior xhior assert pulse width - (ap + 5) 16.6 *1 - ns t 325 xhior xhior xhior negate pulse width - (np + 3) 16.6 *1 - ns t 326 xhior xhcs0 xhcs0 hold time 20 - - ns t 327 hdd xhior data setup time 10 - - ns t 328 xhior hdd data hold time 0 - - ns t 329 hiordy assert xhior xhior output delay time - - 40 ns *1: for more information, refer to the register description, ?ide transfer mode.? stable stable xhcs0(o) hda[2:0](o) xhior(o) hdd[15:0](i) hiordy(i) t 324 t 321 t 326 t 325 t 322 t 327 t 328 t 329 t 323 direction of data transfer S1R72003 data
S1R72003 technical manual 84 epson rev.1.0 9.4.2.2 pio write timing symbol description min. typ. max. unit t 331 xhcs0 hda hda output delay time - 0 - ns t 332 xhcs0 hda hda hold time - 0 - ns t 333 xhcs0 xhiow xhcs0 setup time 60 - - ns t 334 xhiow xhiow xhiow assert pulse width - (ap + 5) 16.6 *1 - ns t 335 xhiow xhiow xhiow negate pulse width - (np + 3) 16.6 *1 - ns t 336 xhiow xhcs0 xhcs0 hold time 20 - - ns t 337 xhiow hdd data output delay time 0 - 20 ns t 338 xhiow hdd data bus negate time 40 - 60 ns t 339 hiordy assert xhiow xhiow output delay time - - 40 ns *1: for more information, refer to the register description, ?ide transfer mode.? valid valid xhcs0(o) hda[2:0](o) xhiow(o) hdd[15:0](o) hiordy(i) t 334 t 333 t 336 t 335 t 332 t 337 t 338 t 339 t 331 direction of data transfer S1R72003 data
S1R72003 technical manual rev.1.0 epson 85 9.4.2.3 dma read timing symbol description min. typ. max. unit t 341 xhcs , hda xhdmack address setup time 60 - - ns t 342 xhior xhcs , hda address hold time 25 - - ns t 343 hdmarq xhdmack xhdmack response time 0 - - ns t 344 xhior hdmarq negate hdmarq hold time 0 - - ns t 345 xhdmack xhior xhdmack setup time 0 - - ns t 346 xhior xhior xhior assert pulse width - (ap + 5) 16.6 *1 - ns t 347 xhior xhior xhior negate pulse width - (np + 3) 16.6 *1 - ns t 348 xhior xhdmack xhdmack hold time 20 - - ns t 349 hdd xhior data setup time 10 - - ns t 34a xhior hdd data bus hold time 0 - - ns *1: for more information, refer to the register description, ?ide transfer mode.? stable stable xhcs[1:0](o) hda[2:0](o) hdmarq(i) xhdmack(o) xhior(o) hdd[15:0](i) t 343 t 341 t 345 t 346 t 347 t 348 t 342 t 349 t 34a t 344 direction of data transfer S1R72003 data
S1R72003 technical manual 86 epson rev.1.0 9.4.2.4 dma write timing symbol description min. typ. max. unit t 351 xhcs , hda xhdmack address setup time 60 - - ns t 352 xhiow xhcs , hda address hold time 20 - - ns t 353 hdmarq xhdmack xhdmack response time 0 - - ns t 354 xhiow hdmarq negate hdmarq hold time 0 - - ns t 355 xhdmack xhiow xhdmack setup time 0 - - ns t 356 xhiow xhiow xhiow assert pulse width - (ap + 5) 16.6 *1 - ns t 357 xhiow xhiow xhiow negate pulse width - (np + 3) 16.6 *1 - ns t 358 xhiow xhdmack xhdmack hold time 20 - - ns t 359 xhiow hdd data output delay time 0 - 20 ns t 35a xhiow hdd data bus negate time 20 - 40 ns *1: for more information, refer to the register description, ?ide transfer mode.? valid valid xhcs[1:0](o) hda[2:0](o) hdmarq(i) xhdmack(o) xhiow(o) hdd[15:0](o) t 353 t 351 t 355 t 356 t 357 t 358 t 352 t 359 t 35a t 354 direction of data transfer S1R72003 data
S1R72003 technical manual rev.1.0 epson 87 9.4.2.5 ultra dma read timing symbol description min. typ. max. unit t 361 xhcs , had xhdmack address setup time 20 - - ns t 362 hdmarq xhdmack xhdmack response time 0 - - ns t 363 xhdmack xhior(w) envelope time 20 - 55 ns t 364 hdd hiordy data setup time 6 - - ns t 365 hiordy hdd data hold time 6 - - ns t 366 hiordy hiordy hiordy cycle time - (cyc + 2) 16.6 *1 - ns t 367 hiordy hiordy hiordy cycle time 2 - t 366 2 - ns t 368 xhior hiordy last strobe time - - 60 ns *1: for more information, refer to the register description, ?ide ultra-dma transfer mode.? xhcs[1:0](o) hda[2:0](o) hdmarq(i) xhdmack(o) xhiow(o) hdd[15:0](i) stable t 362 xhior(o) hiordy(i) t 361 t 364 t 365 t 363 t 363 t 368 t 366 t 366 t 367 initiating host pausing (stop) (hdmardy) (dstrobe) direction of data transfer S1R72003 data
S1R72003 technical manual 88 epson rev.1.0 ultra dma read timing (continued from the preceding page) symbol description min. typ. max. unit t 371 xhior xhiow time till stop assert 100 - - ns t 372 xhior hiordy last strobe time - - 60 ns t 373 xhiow hdmarq interlock time with limit - - 100 ns t 374 hdmarq hdd output delay time 20 - - ns t 375 hdmarq xhdmack minimum interlock time 20 - - ns t 376 hiordy xhdmack minimum interlock time 20 - - ns t 377 xhdmack xhcs0,1 xhcs0,1 hold time 20 - - ns t 378 hdd(crc) xhdmack crc data setup time 6 - - ns t 379 xhdmack hdd(crc) crc data hold time 6 - - ns t 37a hdmarq xhior interlock time with limit 0 - 100 ns t 37b hiordy xhdmack minimum interlock time 20 - - ns xhcs[1:0](o) hda[2:0](o) hdmarq(i) xhdmack(o) xhiow(o) hdd[15:0](o) xhior(o) hiordy(i) t 377 t 371 t 372 t 373 t 375 t 376 t 378 t 379 crc host terminating device terminating t 377 t 379 t 378 t 374 t 37a t 37b (stop) (xhdmardy) (dstrobe) t 374 crc stable (crc) direction of data transfer S1R72003 data stable crc
S1R72003 technical manual rev.1.0 epson 89 9.4.2.6 ultra dma write timing symbol description min. typ. max. unit t 381 xhcs , hda xhdmack address setup time 20 - - ns t 382 hdmarq xhdmack xhdmack response time 0 - - ns t 384 xhdmack xhiow envelope time 20 - 40 ns t 385 xhiow hiordy interlock time with limit 0 - 100 ns t 386 hiordy xhior interlock time without limit 0 - - ns t 387 hdd xhior data setup time 6 - - ns t 388 xhior hdd data hold time 6 - - ns t 389 xhior xhior xhior cycle time - (cyc + 2) 16.6 *1 - ns t 38a xhior xhior xhior cycle time 2 - t 389 2 - ns t 38b hiordy xhior last strobe time - - 60 ns *1: for more information, refer to the register description, ?ide ultra-dma transfer mode.? xhcs[1:0](o) hda[2:0](o) hdmarq(i) xhdmack(o) xhiow(o) hdd[15:0](o) hiordy(i) xhior(o) valid t 381 t 384 t 385 t 386 t 387 t 388 t 389 t 38a t 389 initiating device pausing t 382 t 38b (stop) (hstrobe) (xddmardy) direction of data transfer S1R72003 data
S1R72003 technical manual 90 epson rev.1.0 9.4.3 general-purpose port i/f timing 9.4.3.1 dma read timing (master mode) symbol description min. typ. max. unit t 391 hdmarq xhdmack xhdmack response time 0 - - ns t 392 xhior hdmarq negate hdmarq hold time 0 - - ns t 393 xhdmack xhior xhdmack setup time 0 - - ns t 394 xhior xhior xhior assert pulse width - * 1 - ns t 395 xhior xhior xhior negate pulse width - * 1 - ns t 396 xhior xhdmack xhdmack hold time 20 - - ns t 397 hdd xhior data setup time 10 - - ns t 398 xhior hdd data bus hold time 0 - - ns *1: according to register settings. for details, see the following table and register description ?ide transfer mode? or ?ide config_0?. symbol ide_tmod ideconfig_0.notide * 1 0 (ap+5) * 16.6 t 394 ap 1 (ap+2) * 16.6 0 (np+3) * 16.6 t 395 np 1 (np+2) * 16.6 stable stable hdmarq(i) xhdmack(o) xhior(o) hdd[15:0](i) t 391 t 393 t 394 t 395 t 396 t 397 t 398 t 392 direction of data transfer S1R72003 data
S1R72003 technical manual rev.1.0 epson 91 9.4.3.2 dma write timing (master mode) symbol description min. typ. max. unit t3a1 hdmarq xhdmack xhdmack response time 0 - - ns t3a2 xhiow hdmarq negate hdmarq hold time 0 - - ns t3a3 xhdmack xhiow xhdmack setup time 0 - - ns t3a4 xhiow xhiow xhior assert pulse width - *1 - ns t3a5 xhiow xhiow xhior negate pulse width - *1 - ns t3a6 xhiow xhdmack xhdmack hold time 20 - - ns t3a7 xhiow hdd data output delay time 0 - 25 ns t3a8 xhiow hdd data bus negate time 6 - 40 ns *1: according to register settings. for details, see the following table and register description ?ide transfer mode? or ?ide config_0?. symbol ide_tmod ideconfig_0.notide * 1 0 (ap+5) * 16.6 t 3a4 ap 1 (ap+2) * 16.6 0 (np+3) * 16.6 t 3a5 np 1 (np+2) * 16.6 valid valid hdmarq(i) xhdmack(o) xhiow(o) hdd[15:0](o) t 3a1 t 3a3 t 3a4 t 3a5 t 3a6 t 3a7 t 3a8 t 3a2 direction of data transfer S1R72003 data
S1R72003 technical manual 92 epson rev.1.0 9.4.3.3 dma read timing (slave mode) symbol description min. typ. max. unit t 301 xhiow xhdmack xhiow setup time 5 - - ns t 302 xhdmack xhiow xhiow hold time 5 - - ns t 303 xhior hdmarq negate hdmarq negate delay time 0 25 37 ns t 304 xhdmack xhior xhdmack setup time 0 - - ns t 305 xhior xhior xhior assert pulse width 25 - - ns t 306 xhior xhdmack xhdmack hold time 0 - - ns t 307 xhior hdd data output delay time *1 0 - 25 ns t 308 xhior hdd(hi-z) data bus negate time *1 6 - 40 ns *1: data is output to hdd only when both xhdmack and xhior are asserted. except the above period, hdd enters the input mode. direction of data transfer valid valid hdmarq(o) xhdmack(i) xhior(i) hdd[15:0](o) t 305 t 304 t 301 t 306 t 308 xhiow(i) t 303 t 307 t 302 (pdreqlevel=1) S1R72003 data
S1R72003 technical manual rev.1.0 epson 93 9.4.3.4 dma write timing (slave mode) symbol description min. typ. max. unit t 311 xhior xhdmack xhior setup time 5 - - ns t 312 xhdmack xhior xhior hold time 5 - - ns t 313 xhiow hdmarq negate hdmarq negate delay time 0 25 37 ns t 314 xhdmack xhiow xhdmack setup time 0 - - ns t 315 xhiow xhiow xhiow assert pulse width 25 - - ns t 316 xhiow xhiow xhiow negate pulse width 25 - - ns t 317 xhiow xhdmack xhdmack hold time 0 - - ns t 318 hdd xhiow data setup time 10 - - ns t 319 xhiow hdd data hold time 0 - - ns stable stable hdmarq(o) xhdmack(i) xhior(i) hdd[15:0](i) t 315 t 314 t 311 t 316 t 318 t 319 xhiow(i) t 313 t 317 t 312 (pdreqlevel=1) direction of data transfer S1R72003 data
S1R72003 technical manual 94 epson rev.1.0 9.4.4 usb i/f timing conforms to usb 2.0 specification.
S1R72003 technical manual rev.1.0 epson 95 10. external package plastic qfp15-100 index 14 0.1 51 75 76 50 16 0.4 14 0.1 26 100 1 25 0.18 -0.05 1.7max 0.1 1 .4 0.1 1 0.125 -0.025 0.5 0.2 10 0 +0.1 0.5 +0.05 unit : mm 16 0.4
S1R72003 technical manual 96 epson rev.1.0 appendix-a. usb operation other than transfer a.1 suspend detection a.1.1 suspend detection (hs mode) if no sending and receiving are detected for 3 ms or more (t 1 ) when this ic operates in hs mode, the mode automatically moves to the fs mode (the hs termination is disabled and the fs termination (rpu) is enabled). this operation sets the dp line to ?h?, and ?j? can be checked in usbstatus.linestate[1.0] (if ?se0? is detected, note that reset (described later) occurs). subsequently, if ?j? is still detected at t 2 , the sieintstat. dectectsuspend bit is set. on this occasion, because the xint signal is asserted at the same time, judge that the state is a usb suspend state and, subsequently, enter snooze (pll halt mode) processing until t 4 . however, self-powered products may not be snoozed (fig. a.1 shows the operation when snooze was performed). fig. a.1 suspend timing (hs mode) snooze xcvrselect termselect time t 3 t 1 linestate[1:0] dp / dm last activity soft se0 se1 t 0 t 2 t 4 internal clock t 5 fully meet usb2.0 required frequency 'j' state 'j' state device is suspended hs mode fs mode detectsuspend disbusdetect
S1R72003 technical manual rev.1.0 epson 97 table a.1 suspend timing values (hs mode) timing parameter description value t 0 last bus activity 0 (reference) t 1 if there is no bus activity yet on this occasion, xcvrselect and termselect are set to ?1? and the hs mode is switched to the fs mode. hs reset t 0 + 3.0ms < t 1 {t wtrev } < hs reset t 0 + 3.125ms t 2 linestate[1:0] is sampled. at this time, detectsuspend is set to ?1? and this state is judged as a usb suspend state. t 1 + 100 s < t 2 {t wtwrsths } < t 1 + 875 s t 3 resume must not be issued before this. hs reset t 0 + 5ms {t wtrsm } t 4 snooze is set to ?1?, thereby completely moving to snooze. subsequently, the current exceeding the suspend current specified in usb must not be pulled from vbus. (before moving to snooze, disbusdetect is set to ?1?.) hs reset t 0 + 10ms {t 2susp } t 5 an internal clock is completely halted. (snooze current of 8 ma (typ.)) t 5 < t 4 + 10 s note: { } is a name standardized in the usb2.0 specifications.
S1R72003 technical manual 98 epson rev.1.0 a.1.2 suspend detection (fs mode) if no sending and receiving are detected for 3 ms or more (t 1 ) when this ic operates in hs mode or if ?j? continues being detected in usbstatus.linestate[1:0] (t 1 ) and ?j? is still detected at t2, it is detected that the state is a usb suspend state and the sieintstat.dectectsuspend bit is set. on this occasion, because the xint signal is asserted at the same time, judge that this state is a usb suspend state and, subsequently, enter snooze (pll halt mode) processing until t 4 . however, self-powered products may not be snoozed (fig. a.2 shows the operation when snooze was performed). fig. a.2 suspend timing (fs mode) table a.2 suspend timing values (fs mode) timing parameter description value t 0 last bus activity 0 (reference) t 1 there is no bus activity yet at this point. t 0 + 3.0ms < t 1 {t wtrev } < t 0 + 3.125ms t 2 linestate[1:0] is sampled. at this time, if ?j?, detectsuspend is set to ?1? and this state is judged as a usb suspend state. t 1 + 100 s < t 2 {t wtwrsths } < t 1 + 875 s t 3 resume must not be issued before this. t 0 + 5ms {t wtrsm } t 4 snooze is set to ?1? , thereby completely moving to snooze. subsequently, the current exceeding the suspend current specified in usb must not be pulled from vbus. (before moving to snooze, disbusdetect is set to ?1?.) t 0 + 10ms {t 2susp } t 5 an internal clock is completely halted. (snooze current of 8 ma (typ.)) t 5 < t 4 + 10 s note: { } is a name standardized in the usb2.0 specifications. detectsuspend xcvrselect termselect time t 3 t 1 linestate[1:0] dp / dm t 0 t 2 t 4 internal clock t 5 fully meet usb2.0 required frequency 'j' state 'j' state device is suspended fs mode snooze disbusdetect last activity
S1R72003 technical manual rev.1.0 epson 99 a.2 reset detection a.2.1 reset detection (hs mode) if no sending and receiving are detected for 3 ms or more (t 1 ) when this ic operates in hs mode, the mode automatically moves to the fs mode (the hs termination is disabled and the fs termination (rpu) is enabled). even if this operation is performed, the dp line is kept being set to ?l?. as a result, ?se0? can be detected even in usbstatus.linestate[1:0]. when ?se0? is still detected at t 2 , the siwintstat.detectreset bit is set. on this occasion, because the xint signal is asserted at the same time, judge that this is a reset indication. subsequently, after setting the usbcontrol.disbusdetect bit, perform hs detection handshake (described later). fig. a.3 reset timing (hs mode) table a.3 reset timing values (hs mode) timing parameter description value t 0 last bus activity 0 (reference) t 1 if there is no bus activity yet at this point, xcvrselect and termselect are set to ?1? and the hs mode is switched to the fs mode. hs reset t 0 + 3.0ms < t 1 {t wtrev } < hs reset t 0 + 3.125ms t 2 linestate[1:0] is sampled. at this time, if ?se0?, detectsuspend is set to ?1? and this state is judged as a move to reset. after a reset indication is detected, disbusdetect is set to ?1? and, subsequently, hs detection handshake is performed. t 1 + 100us < t 2 {t wtwrsths } < t 1 + 875 s note: { } is a name standardized in the usb2.0 specifications. xcvrselect termselect time t 1 linestate[1:0] dp / dm last activity driven se0 se1 t 0 t 2 se0 hs mode fs mode hs detection handshake detectreset disbusdetect
S1R72003 technical manual 100 epson rev.1.0 a.2.2 reset detection (fs mode) if ?se0? continues being detected in usbstatus.linestate[1:0] for 2.5 s (t 1 ) when this ic operates in fs mode, the sieintstat.detectreset bit is set. on this occasion, because the xint signal is asserted at the same time, judge that this is a reset indication. subsequently, after setting the usbcontrol.disbusdetect bit, perform hs detection handshake (described later). fig. a.4 reset timing (fs mode) table a.4 reset timing values (fs mode) timing parameter description value t -1 last bus activity t 0 a reset indication starts from a downstream port. 0 (reference) t 1 when ?se0? is continuing, detectreset is set to ?1? and this state is judged as a move to reset. after a reset indication is detected, disbusdetect is set to ?1? and, subsequently, hs detection handshake is performed. hs reset t 0 + 2.5 s < t 2 {t wtrev } < note: { } is a name standardized in the usb2.0 specifications. xcvrselect termselect time t 0 linestate[1:0] dp / dm t -1 fs mode driven se0 'j' state t 1 'j' state se0 hs detecion handshake detectreset disbusdetect last activity
S1R72003 technical manual rev.1.0 epson 101 a.3 hs detection handshake high-speed detection handshake is started from any one of the three states in snooze/sleep, fs operation, or hs operation by asserting ?se0? from a downstream port (when reset is started from the above state). do not move to the hs detection handshake for 4 ms from the reset start. for details, see the usb2.0 specifications. this section describes the method of moving from the above three states to the hs detection handshake. 1) if ?se0? is detected on a bus when this ic is in the snooze/sleep state: subsequently, move to hs detection handshake. 2) if ?se0? exceeding 2.5 s is detected when this ic is operating in fs mode: subsequently, move to hs detection handshake. 3) if ?se0? exceeding 3.0 ms is detected when this ic is operating in hs mode: in the hs mode, first, because it must be judged that this state is a usb suspend state or reset, the mode must be switched to the fs mode once. accordingly, by switching both bits xcvrcontrol.xcvrselect and xcvrcontrol.termselect to the fs mode, the hs termination is disabled and the fs termination is enabled. these modes must be switched within 3.125 ms. check usbstatus.linestate[1:0] between 100 s or more and less than 875 s after this mode switching. if ?j?, judge that this state is as a usb suspend state and if ?se0?, judge it as reset. at this time, when the state is judged as the reset, subsequently, move to hs detection handshake. in either case, the reset exists for 10 ms at a minimum, but the timing slightly differs according to the state (hs or fs) before move. here, the time the reset was started is defined as ?hs reset t 0 ? and, subsequently, the operation from this ?hs reset t 0 ? is described. in the above case 3), the ic is in operation, an internal clock is also stable sufficiently, thereby causing no problem, but attention needs to be paid to the cases 1) and 2). in the case 1), the ic enters the snooze/sleep state and an internal clock may not be output when the reset is detected. to output the internal clock so that hs detection handshake can be performed, pm control.analogpwdown, pm control. snooze, and pmcontrol.pllsel are all set to ?0?, that is, pll480 must operate. when pmcontrol. snooze is set from ?1? to ?0?, a fixed pll stable time is necessary. further, if the state moves to the sleep state, an oscillation stable time is necessary. (this oscillation stable time varies according to the status of an oscillator and an oscillator circuit). in the case 2), the ic operates in fs mode and the internal clock is also stable fully. on this occasion, when pllsel selects pll60, the pll stable time is necessary in the same manner as 1). because the pll stable time is very short, it needs not to be conscious of much. however, because the oscillation stable time is in a unit of several ms, attention must be paid extremely.
S1R72003 technical manual 102 epson rev.1.0 a.3.1 when this ic is connected to fs downstream port the operation when this ic is connected to a downstream port that does not support hs is shown. when the hs detection handshake starts (t0), both bits xcrvcontrol.xcrvselect and xcrvcontrol.termselect must be set in fs mode (the fs termination, that is, the dp pull up resistor (rpu) is enabled and the hs termination is disabled). first, the usbcontrol.gochirp bit is set. subsequently, xcvrcontrol.opmode[1:0] is set for ?disable bit stuffing and nrzi encoding? and the data padded with ?0? is prepared (t 1 ). this is used to issue ?hs k? (chirp) onto a bus. further, at the same time, when xcrvcontrol.xcrvselect bit is set in hs mode and set in the ready for sending state, ?hs k? (chirp) is issued to the downstream port. after it is issued, a chirp is awaited from the downstream port (t 2 ). usually, the downstream port that supports hs continuously issues ?hs k? and ?hs j? from t 3 (described later). however, when the downstream port does not support hs (this time), no chirp is issued even at t 4 , the xcrvcontrol.xcrvselect bit is automatically switched to the fs mode and the usbcontrol.gochirp bit is cleared. at the same time, the usbstatus.fsxhs bit is set and the sieintstat.chirpcmp bit is set. on this occasion, because the xint signal is asserted at the same time, judge that hs detection handshake terminated. fig. a.5 hs detection handshake timing (fs mode) time t 0 upstream port actions device actions t 1 xcvrselect termselect linestate[1:0] dp / dm se0 gochirp se0 upstream port chirp fs mode t 2 'k' state device k chirpcmp 'j' state 'j' state t 3 t 4 t 5 t 6 no downstream port chirps opmode[1:0] disable bs and nrzi normal operation normal disbusdetect sof
S1R72003 technical manual rev.1.0 epson 103 table a.5 hs detection handshake timing values (fs mode) timing parameter description value t 0 hs detection handshake starts. 0 (reference) t 1 the hs transceiver is enabled and gochirp is set to ?1?, then chirp k starts being issued. t 0 < t 1 < hs reset t 0 + 6.0ms t 2 the issue of chirp k terminates. it must be issued for a minimum of 1 ms. t 1 + 1.0ms {t uch } < t 2 < hs reset t 0 + 7.0ms {t uchend } t 3 when the downstream port supports hs, chirp k starts being issued from here. t 2 < t 3 < t 2 + 100 s {t wtdch } t 4 if no chirp can be detected, at this point, the mode returns to the fs mode and chirpcmp is set to ?1?, then it is awaited that the reset sequence terminates. t 2 + 1.0ms < t 4 {t wtfs } < t 2 + 2.5ms t 5 end of the reset sequence hs reset t 0 + 10ms {t drst (min.)} t 6 normal operation in fs mode t 6 note: { } is a name standardized in the usb2.0 specifications. note: to generate chirp k for a minimum of 1 ms, judge at 66,000 cycles (internal clock: 60 mhz).
S1R72003 technical manual 104 epson rev.1.0 a.3.2 when this ic is connected to hs downstream port the operation when this ic is connected to a downstream port that does not support hs is shown. when hs detection handshake starts (t0), both bits xcrvcontrol.xcrvselect and xcrvcontrol.termselect must be set in fs mode (the fs termination, that is, the dp pull up resistor (rpu) is enabled and the hs termination is disabled). first, the usbcontrol.gochirp bit is set. subsequently, xcvrcontrol.opmode[1:0] is set for ?disable bit stuffing and nrzi encoding? and the data padded with ?0? is prepared (t 1 ). this is used to issue ?hs k? (chirp) onto a bus. at the same time, when xcrvcontrol.xcrvselect bit is set in hs mode and set in the ready for sending state, ?hs k? (chirp) is issued to the downstream port. after it is issued, a chirp is awaited from the downstream port (t 2 ). thereupon, because the downstream port supports hs, hs k? (chirp k) and ?hs j? (chirp j) are alternately issued continuously (t 3 ). when this state is detected six times as chirp k-j-k-j-k-j in usbstatus.linestate[1:0] (t 6 ), the xcvrcontrol.termselect bit is automatically switched to the hs mode (t 7 ) and moves to the perfect hs mode. simultaneously with this, the usbcontrol.gochirp bit is cleared. at the same time, the usbstatus.fsxhs bit is set and the sieintstat.chirpcmp bit is set. on this occasion, because the xint signal is asserted at the same time, judge that hs detection handshake terminated. this chirp k or chirp j from the downstream port is recognized as a bus activity and must not be judged as a usb suspend state. hence, in the hs mode, this chirp k or chirp j is detected sequentially and fetched in an internal suspend timer. besides, to detect chirp k-j-k-j-k-j, usbstatus.linestate[1:0] is used. unlike a usual hs packet, because chirp k and chirp j are very slow, they can be detected in usbstatus.linestate[1:0]. however, if a bus signal is loaded on usbstatus.linestate[1:0] when an original packet is received, the signal is very noisy. accordingly, when termselect is in hs mode, usbstatus.linestate[1:0] outputs ?se1?. fig. a.6 shows that the hs termination at the device side is enabled because the height of chirp varies at t 6 . usually, the chirp when termselect is in fs mode is about 800 mv and the chirp (equally in the hs normal sending and receiving packet) when termselect is in hs mode is about 400 mv.
S1R72003 technical manual rev.1.0 epson 105 fig. a.6 hs detection handshake timing (hs mode) table a.6 hs detection handshake timing values (hs mode) timing parameter description value t 0 hs detection handshake starts. 0 (reference) t 1 the hs transceiver is enabled and gochirp is set to ?1?, then chirp k starts being issued. t 0 < t 1 < hs reset t 0 + 6.0ms t 2 the issue of chirp k terminates. it must be issued for a minimum of 1 ms. t 1 + 1.0ms {t uch } < t 2 < hs reset t 0 + 7.0ms {t uchend } t 3 the downstream port issues the first chirp k to a bus. t 2 < t 3 < t 2 + 100 s {t wtdch } t 4 the downstream port switches chirp k to chirp j and issues chirp j. t 3 + 40 s {t dchbit (min.)} < t 4 < t 3 + 60 s { t dchbit (max.)} t 5 the downstream port switches chirp j to chirp k and issues chirp k. t 4 + 40 s {t dchbit (min.)} < t 5 < t 4 + 60 s { t dchbit (max.)} t 6 chirp k-j-k-j-k-j is detected. t 6 t 7 when chirp k-j-k-j-k-j is detected, the fs termination is disabled and the hs termination is enabled. chirpcmp is set to ?1?. further, reset termination is awaited. t 6 < t 7 < t 6 + 500 s t 8 recognized as a bus activity using chirp k or chirp j. however, because sync cannot be detected, it is not recognized that the packet is being received. t 8 t 9 the issue of chirp k or chirp j terminates from the downstream port. t 10 - 500 s {t dchse0 (max.)} < t 9 < t 10 - 100 s{t dchse0 (min.)} t 10 end of the reset sequence hs reset t 0 + 10ms {t drst (min.)} note: { } is a name standardized in the usb2.0 specifications. note: to generate chirp k for a minimum of 1 ms, judge at 66,000 cycles (internal clock: 60 mhz). time t 0 upstream port actions device actions t 1 xcvrselect termselect linestate[1:0] dp / dm se0 gochirp upstream port chirp t 2 'k' state device k chirpcmp t 3 t 6 t 9 t 10 downstream port chirps opmode[1:0] disable bs and nrzi normal operation normal t 4 t 5 kk jj t 7 se0 se0 sof kj t 8 kj j kkj se1 se0 hs mode disbusdetect
S1R72003 technical manual 106 epson rev.1.0 a.3.3 when this ic is reset in snooze when this ic is in the snooze state, an internal clock is also output. here, an oscillator circuit is assumed to operate (not in the sleep state but in the snooze state) and the operation is described. the pmcontrol.snooze bit affects only the pll operation and will not affect the oscillator circuit. accordingly, when the pmcontrol.snooze bit is set from ?1? to ?0?, the pll powerup time is necessary. when the ic is in the snooze state and reset is detected (t 0 ), the sieintstat.nonj bit is set and, at the same time, the xint signal is asserted. clear the pmcontrol. snooze to ?0? so that the ic can be recovered from snooze and immediately enter the reset sequence (t 1 ). after the powerup time elapses (t 2 ), the pmcontrol. insnooze bit is cleared, and, at the same time, an internal starts being output. subsequently, perform hs detection handshake (described later). at this time, if the oscillator circuit is not halted (not recovered from the snooze state), the internal clock is output at the frequency accuracy that conforms to the usb2.0 specifications. fig. a.7 hs detection handshake timing from suspend upstream port chirp time t 0 upstream port actions device actions t 3 xcvrselect termselect linestate[1:0] dp / dm se0 pll powerup time t 4 'k' state device k opmode[1:0] disable bs and nrzi normal se0 se0 snooze internal clock j t 1 t 2 fully meet usb2.0 required frequency se0 look for downstream chirps j non_j insnooze disbusdetect gochirp
S1R72003 technical manual rev.1.0 epson 107 table a.7 hs detection handshake timing values from suspend timing parameter description value t 0 when non_j is set to ?1? and ?se0? is checked in linestate[1:0], the reset in snooze is detected. 0 (hs reset t 0 ) t 1 after the reset is detected, snooze is cleared to ?0?. t 1 t 2 insnooze is set to ?0?. the internal clock output is stable. t 1 + 250 s < t 2 t 3 gochirp is set to ?1? and chirp k is issued to a bus. (before chirp k is issued, disbusdetect is set to ?1?.) t 2 < t 3 < hs reset t 0 + 5.8ms t 4 the issue of chirp k terminates. t 3 + 1.0ms {t uch } < t 4 < hs reset t 0 + 7.0ms {t uchend } note: { } is a name standardized in the usb2.0 specifications. note: to generate chirp k for a minimum of 1 ms, judge at 66,000 cycles (internal clock: 60 mhz). note: the case (sleep state) where the oscillator circuit is also halted is described later (in addition to the pll powerup ti me, the osc powerup time is necessary).
S1R72003 technical manual 108 epson rev.1.0 a.4 issue of resume this section describes a method of resuming itself for some reason when a remote wakeup is supported and this remote wake-up is enabled from a host. however, the remote wakeup can be performed at least after 5 ms elapse when a bus becomes idle. further, before a lapse of 10 ms after a resume signal is issued, the current before a device enters the usb suspend state cannot be pulled from vbus. the device is first recovered from snooze/sleep to wake up. the sieintenb.ennonj bit is cleared and the pmcontrol.snooze bit is cleared (t 0 ). after the pll powerup time elapses (t 1 ), the pmcontrol. insnooze bit is cleared and, at the same time, an internal clock starts being output. at this time, if an oscillator circuit is halted, this internal clock is output at the frequency accuracy that conforms to the usb2.0 specifications. subsequently, the usbcontrol.sendwakeup bit is set and a resume signal is issued (t 2 ). at this time, internally, xcrvcontrol.opmode[1:0] is set for ?disable bit stuffing and nrzi encoding? and ?0? is prepared as transmission data. a packet sending state is set and ?k? (resume signal) is issued. a downstream port detects this resume signal and returns ?k? (resume signal) onto a bus (t 3 ). after about 1 ms when the resume signal starts being issued, the resume signal that was issued to the bus by clearing the usbcontrol.sendwakeup bit is halted t 4 ). however, at this point, the downstream port still holds the bus in the resume signal. then the usbconstrol.restoreusb bit is set. after a fixed time elapses, the downstream port stops the issue of the resume signal (t 5 ) and is switched to the speed mode before usb suspend. when this is detected (not ?k?), both bits xcrvcontrol.xcrvselect and xcrvcontrol.termselect are switched to a desired mode (hs mode at this time) and the usbcontrol.restoreusb bit is cleared. simultaneously, the sieintstat.restorecmp bit is set and, at the same time, the xint signal is asserted. here, when the usb suspend starts, the speed mode (hs or fs) is stored as the usbstatus.fsxhs bit. when a device is recovered using resume, the mode that this usbstatus.fsxhs bit indicates is set. hs detection handshake is not necessary every resume. note that only the case where the mode before the usb suspend was in the hs mode is described here. actually, in the fs mode, the normal fs mode occurs at t5 or later and there is no great sequence change in particular. when this ic is in the snooze state (the pmcontrol. snooze bit is ?1?), an internal clock is not output. the operation is described here, assuming that an oscillator circuit operates (not in the sleep state but the snooze state). the pmcontrol. snooze bit affects only the pll operation and will not affect the operation of the oscillator circuit. accordingly, when the pmcontrol. snooze bit is cleared, the pll powerup time is necessary. if the oscillator circuit is also halted in snooze (in the sleep state and the oscillator circuit stops), the osc powerup time is also necessary in addition to the pll powerup time. this osc powerup time is described later.
S1R72003 technical manual rev.1.0 epson 109 fig. a.8 assert resume timing (hs mode) time t 0 upstream port actions device actions t 4 xcvrselect termselect linestate[1:0] dp / dm 'j' state pll powerup time t 5 'k' state opmode[1:0] disable bs and nrzi normal snooze internal clock fs idel ('j' state) t 2 fully meet usb2.0 required frequency se1 hs mode t 1 t 3 resume signal ('k' state) t 6 upstream resume downstream resume fs mode se0 se0 ennon_j insnooze sendwakeup restoreusb restorecmp
S1R72003 technical manual 110 epson rev.1.0 table a.8 assert resume timing values (hs mode) timing parameter description value t 0 resume starts. snooze is cleared to ?o?. (before resume starts, ennon_j is cleared to ?0?.) 0 (reference) t 1 insnooze is set to ?0?. the internal clock output becomes stable. t 0 + 250 s < t 1 t 2 sendwakeup is set to ?1? and ?k? of fs starts being issued. here, the current before usb suspend must not be pulled within 10 ms. t 0 < t 2 < t 0 + 10ms t 3 the downstream port returns ?k? of fs. t 2 < t 3 < t 2 + 1.0ms t 4 sendwakeup is cleared to ?0? and the issue of ?k? of fs terminates. after ?k? is checked using linestate[1:0], restoreusb is set to ?1?. t 2 + 1.0ms {t drsmup (min.)} < t 4 < t 2 + 15ms {t drsmup (max.)} t 5 the downstream port terminates the issue of ?k? of fs. t 2 + 20ms {t drsmdn } t 6 restorecmp is set to ?1?. when the mode before usb suspend is the hs mode, it automatically moves to the hs mode. t 5 + 1.33 s {2 low-speed bit times} note: { } is a name standardized in the usb2.0 specifications.
S1R72003 technical manual rev.1.0 epson 111 a.5 detection of resume when this ic is snoozed, ?j? (usbstatus.linestate[1.0] is ?j?) is observed on a bus. when ?k? is observed on the bus, ?k? is issued from the downstream port, and, at this time, a wakeup indication (resume indication) might have been received (t 0 ). at this time, if an oscillator circuit does not stop the operation (not in the sleep state), the sieintstat.nonj bit is set and, at the same time, the xint signal is asserted. first, the pmcontrol. snooze bit is cleared to ?0? (t 1 ). after the pll powerup time elapses, the pmcontrol. insnooze bit is cleared, and, at the same time, an internal clock starts being output. at this time, if an oscillator circuit is halted, this internal clock is output at the frequency accuracy that conforms to the usb2.0 specifications. then the usbcontrol.restoreusb bit is set. after a fixed time elapses, the downstream port stops the issue of the resume signal (t 5 ) and is switched to the speed mode before usb suspend. when this is detected (not ?k?), both bits xcrvcontrol.xcrvselect and xcrvcontrol.termselect are switched to a desired mode (hs mode at this time) and the usbcontrol.restoreusb bit is cleared. simultaneously, the sieintstat.restorecmp bit is set and, at the same time, the xint signal is asserted. the operation is described here, assuming that an oscillator circuit operates (not in the sleep state but the snooze state). the pmcontrol. snooze bit affects only the pll operation and will not affect the operation of the oscillator circuit. accordingly, when the pmcontrol. snooze bit is cleared, the pll powerup time is necessary. if the oscillator circuit is also halted in snooze (in the sleep state and the oscillator circuit is halted), the osc powerup time is also necessary in addition to the pll powerup time. this osc powerup time is described later. fig. a.9 detect resume timing (hs mode) time t 0 upstream port actions device actions xcvrselect termselect linestate[1:0] dp / dm j pll powerup time t 3 'k' state snooze internal clock j t 2 fully meet usb2.0 required frequency se1 hs mode t 1 resume signal ('k' state) t 4 downstream resume fs mode se0 se0 non_j insnooze restoreusb restorecmp
S1R72003 technical manual 112 epson rev.1.0 table a.9 detect resume timing values (hs mode) timing parameter description value t 0 the downstream port issues ?k? of fs. non_j is set to ?1?. 0 (reference) t 1 snooze is cleared to ?0?. t 1 t 2 insnooze is set to ?0?. the internal clock output becomes stable. after ?k? is checked in linestate [1:0], restoreusb is set to ?1?. t 1 + 250 s < t 2 t 3 the downstream port terminates the issue of ?k? of fs. at the same time, the downstream port moves to the hs mode before usb suspend. t 2 + 20ms {t drsmdn } t 4 when the mode before usb suspend is the hs mode, it automatically moves to the hs mode. t 5 + 1.33 s {2 low-speed bit times} note: { } is a name standardized in the usb2.0 specifications.
S1R72003 technical manual rev.1.0 epson 113 a.6 cable insertion this section describes the case where a device is connected to a hub or a host, that is, the cable is inserted. when the cable is removed or not connected intentionally, set the hs mode as an initial value for both bits xcvrcontrol.xcvrselect and xcrvcontrol.termselect. when the cable is connected, vbus is set to ?h? and, at the same time, the usbstatus.vbus bit is set (t 0 ). subsequently, when the snooze state is set, clear the pmcontrol. snooze bit (t 1 ). hereupon, if reset applies to a built-in utm by setting the pmcontrol.resetutm bit and clearing it after a fixed time (t 2 ), an internal clock is output before it becomes stable (t 1 to t 3 ). if this operation is not performed, the internal clock is not output. accordingly, wait until the pmcontrol. insnooze bit is cleared. subsequently, first, because the fs device must be connected, set both bits xcrvcontrol.xcvrselect and xcvrcontrol.termselect in the fs mode so that the fs mode can be set once. subsequently, the downstream port issues reset (t 5 ) and, at the same time, hs detection handshake starts. fig. a.10 device attach timing pllsel time t 0 upstream port actions device actions activeusb disbusdetect linestate[1:0] dp / dm clk powerup time t 5 se1 internal clock t 1 fully meet usb2.0 required frequency hs detection handshake se0 (v bus ) resetutm t 3 snooze t 2 t 4 se0 fs idle ('j' state) se0 'j' state select pll480 insnooze xcvrselect termselect '00'(normal mode) opmode[1:0]
S1R72003 technical manual 114 epson rev.1.0 table a.10 device attach timing values timing parameter description value t 0 vbus is valid. 0 (reference) t 1 resetutm is set to ?1?. snooze is cleared to ?0?. the internal clock output starts together with resetutm. t 1 t 2 resetutm is cleared to ?0?. t 1 + 10ns < t 2 t 3 insnooze is set to ?0?. the internal clock output becomes stable. t 2 + 250 s < t 3 t 4 activeusb is set to ?1?. disbusdetect is set to ?1?. termselect and xcvrselect are set to ?1?. opmode[1:0] is set to ?00?. the mode moves to the fs mode. the fs termination is valid. t 0 + 100ms {t sigatt } < t 4 t 5 reset is issued from the downstream port. t 4 + 100ms {t attdb } < t 5 note: { } is a name standardized in the usb2.0 specifications.
S1R72003 technical manual rev.1.0 epson 115 a.7 clock this section describes 1) a recovery method from the case where an oscillator circuit was halted, 2) a method for moving to sleep, and 3) a method for switching a pll (480 mhz system or 60 mhz system) that operates. here, 1) is the processing that is performed in a steady state when the power is on and sleep is released. 2) needs to be aware of extremely because it violates the usb 2.0 specifications depending on an oscillator and an oscillator circuit (built-in) (described later). if this specification time cannot be satisfied, never sleep. 3) aims at further reducing current consumption by switching from a 480 mhz system to a 60 mhz system that is a pll for hs when a device is connected to the downstream port that does not support hs. the device that builds in sufficient power may not be switched. a.7.1 start of oscillator circuit an oscillator circuit is controlled by the xsleep pin and the oscillator circuit is halted when it is asserted. to recover from the sleep state, when the xsleep pin is negated (t 0 ), the oscillator circuit starts oscillating. then the pmcontrol. snooze bit is cleared. once the pmcontrol.resetutm bit is cleared (t 1 , t 2 ), an internal clock starts being output. note that the internal clock is not stable. subsequently, after the osc powerup time (t 3 ) and when the pll powerup time elapses (t 4 ), the internal clock at the frequency 60 mhz 500 ppm required in the usb2.0 specifications is output. here, the pmcontrol.resetutm bit is set once and cleared. however, if this operation is not performed, the internal clock is output (t 4 ) after the pmcontrol. snooze bit is cleared and after the pll powerup time elapses. however, it cannot be guaranteed that this internal clock conforms to the usb2.0 specifications. here, to obtain the internal clock that conforms to the usb2.0 specifications, the clk powerup time (osc powerup time + pll powerup time) are necessary. among them, the osc powerup time requires a unit of several ms according to the conditions of an oscillator and an oscillator circuit. further, the pll powerup time is a very short time as much as about 250 s in comparison with the oscillator circuit. accordingly, to obtain a utm usable clock as quick as possible, this osc powerup time needs to be shortened to the utmost. besides, the utm usable clock is defined as 60mhz 10% and the clk powerup time is defined as 5.6 ms. further, until the frequency 60mhz 500ppm required in the above usb2.0 specifications is obtained, the time is defined as less than 1.4 ms from this clk powerup time. fig. a.11 osc-on timing snooze time osc powerup time t 0 resetutm internal clock t 1 t 2 t 4 pllsel t 3 fully meet usb2.0 required frequency pll powerup time clk powerup time sleep xsleep insnooze
S1R72003 technical manual 116 epson rev.1.0 table a.11 osc-on timing values timing parameter description value t 0 as soon as xsleep is negated, an oscillator circuit starts operation. 0 (reference) t 1 a pll starts operation. resetutm is set to ?1? and snooze is cleared to ?0?. t 1 t 2 resetutm is cleared to ?0?. t 1 + 10ns < t 2 t 3 an oscillator circuit is stable. user defined t 4 insnooze is set to ?0? and a pll (internal clock) is stable. t 3 + 250 s < t 4
S1R72003 technical manual rev.1.0 epson 117 a.7.2 sleep (stop of oscillator circuit) the move to the above snooze was controlled only with the pmcontrol. snooze bit, but to move to sleep, the xsleep pin is controlled further. however, as described in the previous section ?start of oscillator circuit?, when the oscillator circuit is halted, note that the osc powerup time is necessary. an internal clock is halted by setting the pmcontrol. snooze bit (t 0 ). subsequently, if the xsleeppin is asserted when the pmcontrol.sleepwnb bit is set, the oscillator circuit is halted and enters the sleep state. subsequently, to recover from this sleep state, first, the xsleep pin is negated (t 2 ). after the osc powerup time elapses (t 3 ), clear the pmcontrol. snooze bit (t 4 ). after the pll powerup time elapses, an internal clock is output (t 5 ). this internal clock is set to the frequency 60 mhz 500 ppm required in the usb2.0 specifications. fig. a.12 sleep timing table a.12 sleep timing values timing parameter description value t 0 snooze is set to ?1?. a pll is halted and the internal clock output is halted. (before snooze, sleepenb bit is set to ?1?.) 0 (reference) t 1 the xsleep pin is asserted. the oscillator circuit is halted. (sleep current of 1 ma (typ.)) t 1 t 2 the xsleep pin is negated. the oscillator circuit starts operation. t 2 t 3 an oscillator circuit is stable. user defined t 4 snooze is set to ?0?. a pll starts operation. t 4 t 5 a pll is stable. t 4 + 250 s < t 5 xsleep snooze time internal clock sleep t 0 t 1 t 2 t 4 t 3 osc powerup time pll powerup time normal suspend t 5 sleepenb insnooze
S1R72003 technical manual 118 epson rev.1.0 a.7.3 pll switching this ic builds in two plls of 480 mhz and 60 mhz systems. the 480 mhz system can be used in both the hs and fs modes, but the 60 mhz system can be used in only the fs mode. because the pll of this 480 mhz has high current consumption in comparison with the pll of the 60 mhz system. the current consumption can be suppressed greatly by selecting the 60 mhz system in fs mode. this section describes the case where the host and hub connected to an upstream port do not support the hs mode and operate in fs mode after hs detection handshake terminates. in actual, after a device operates in hs mode using the pll of the 480 mhz system and then enters the fs mode, the method of switching the pll of the 480 mhz system to the pll of the 60 mhz system for the purpose of reducing the current consumption is described. when the pmcontrol.pllsel bit is switched from the 480 mhz system to the 60 mhz system, the pll of the 60 mhz system is going to start. on this occasion, because the pll of the 60 mhz system is not operated stably, it cannot be used immediately. accordingly, after the pll powerup time of this 60 mhz system elapses, the internal clock generated from the pll of the 480 mhz system is halted (t 1 ) and is switched to a clock generated from the 60 mhz system and output (t 2 ). at this time, because the phase of both clocks is checked so that a glitch cannot be loaded on the clocks, a circuit that uses these clocks will not be affected greatly. equally, to switch the pmcontrol.pllsel bit from the pll of the 60 mhz system to the pll of the 480 mhz system, when the pmcontrol.pllsel bit is switched from the 60 mhz system to the 480 mhz system, the pll of the 480 mhz system is going to start (t 3 ). on this occasion, because the pll of the 480 mhz system is not operated stably, it cannot be used immediately. accordingly, after the pll powerup time of this 480 mhz system elapses, the internal clock generated from the 60 mhz system is halted (t 4 ) and is switched to the clock generated from the 480 mhz system and output (t 5 ). at this time, because the phase of both clocks is checked so that a glitch cannot be loaded on the clocks, a circuit that uses these clocks will not be affected greatly. fig. a.13 switching pll timing table a.13 switching pll timing values timing parameter description value t 0 pllsel is switched from pll480 to pll60. 0 (reference) t 1 as soon as pll60 becomes stable, the internal clock output from pll480 is halted. t 0 + 250 s < t 1 t 2 the internal clock from pll60 starts being output. t 2 < t1 + 50ns t 3 pllsel is switched from pll60 to pll480. t 3 t 4 as son as pll480 becomes stable, the internal clock output from pll60 is halted. t 3 + 250 s < t 4 t 5 the internal clock from pll480 starts being output. t 5 < t 4 + 50ns pllsel snooze time internal clock clock made from pll480 t 2 t 1 clock made from pll60 clock made from pll480 t 4 t 5 t 0 t 3
S1R72003 technical manual rev.1.0 epson 119 appendix-b. recommended oscillator circuit oscillation characteristics vary according to various conditions (parts used and substrate patterns). because the following recommended circuit constants satisfy the optimum conditions in the nec 72003eva board, use them as reference values. determine the oscillation circuit constants after sufficient evaluation. S1R72003f00b100 99pin 100pin xi 1m xo rd crystal cg cd gnd recommended circuit constant voltage range crystal oscillator made by seiko epson corp. (c l =16pf 50ppm) oscillation frequency (mhz) cg (pf) cd (pf) rd ( ? ) min. (v) max. (v) fa-365 12,16,20,24 22 22 0 3.0 3.6
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first issue december, 2001 printed march, 2002 in japan h a epson electronic devices website electronic devices marketing division oo http://www.epsondevice.com/ S1R72003 technical manual

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